Controller Parallel Processing Secure Computation
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Solution Overview
Problem
Existing computing storage devices face challenges in efficiently processing secure computation tasks, particularly when using fully homomorphic encryption, due to the time-consuming nature of these operations.
Innovation Solution
A controller is designed for a computing storage device that includes a computation processing circuit capable of duplicating input data, executing parallel computation processes using multiple parameters, and outputting results, thereby accelerating secure computation tasks like key-switching multiparty computation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If secure computation is executed using fully homomorphic encryption, then security and privacy protection are improved, but computation time increases significantly
Solution Approach 1:
The computation task is divided into multiple segments that can be processed in parallel. The controller divides the input data into multiple portions and assigns each portion to different computation processing circuits, allowing simultaneous execution of encryption and decryption operations that would traditionally be performed sequentially, thereby reducing overall computation time while maintaining security.
Solution Approach 2:
The patent transitions from single-threaded sequential processing to multi-threaded parallel processing by introducing multiple computation processing circuits. This dimensional change from one-dimensional sequential execution to two-dimensional parallel execution across multiple circuits enables secure computation tasks to be completed faster without compromising the cryptographic security guarantees.
2Measurement precision
If multiple computation parameters are used for secure computation, then computation accuracy and security are improved, but processing time increases
Solution Approach 1:
The patent segments the computation task into multiple independent sub-tasks that can be executed in parallel across different computation processing circuits. Each circuit processes a portion of the data with the required multiple computation parameters, and the results are aggregated at the end, achieving both high computation accuracy and reduced processing time.
Solution Approach 2:
The patent combines multiple computation processing circuits to work simultaneously on different portions of the same computation task. By merging the capabilities of multiple circuits and coordinating their parallel execution, the system achieves the computational accuracy required by multiple parameters while overcoming the time penalty through parallelism.
3Device complexity
If computation processing is executed sequentially, then device complexity is reduced, but productivity decreases
Solution Approach 1:
The patent divides the computation processing into multiple independent segments that can be handled by separate computation processing circuits. This segmentation enables parallel execution of encryption and decryption operations, significantly improving computation throughput while keeping each individual circuit relatively simple in structure.
Solution Approach 2:
The computation processing circuits are designed with multi-functionality to handle both encryption and decryption operations. This universal design allows the same type of circuit to perform multiple functions in parallel, improving productivity without requiring entirely different specialized hardware for each operation, thus balancing complexity and throughput.
Data Source
AI summary
According to one embodiment, a controller includes a first interface configured to receive an I/O command specifying first host data from a host, a second interface configured to transmit and receive the first host data to and from a storage, and a computation processing circuit. The computation processing circuit includes an input circuit configured to input the first host data and plural computation parameters, a duplication processing circuit configured to obtain plural first host data by duplicating the first host data, plural first processing circuits configured to execute computation processes using the input plural parameters for the obtained plural first host data, and an output circuit configured to output computation results.