Controller Parallel Write Scheduling for Memory Idle Period Reduction
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Solution Overview
Problem
Current storage systems experience inefficiencies in write throughput due to cache-busy periods and programming asymmetry between Least Significant Bit (LSB) and Most Significant Bit (MSB) pages, leading to prolonged idle periods and reduced performance.
Innovation Solution
A controller that schedules writing pairs of LSB and MSB pages sequentially to maximize throughput, and introduces artificial random delays to optimize communication idle periods, allowing for efficient selection and ordering of memory devices based on readiness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written sequentially to multiple memory devices without optimization, then device simplicity is maintained, but write throughput is reduced due to prolonged idle periods during cache-busy and programming operations
Solution Approach 1:
The controller predicts programming completion times for multiple memory devices in advance and prepares the write schedule accordingly. By anticipating when each device will be ready to receive subsequent data, the controller can proactively switch between devices to minimize idle periods on the interface, thereby improving write throughput without adding physical complexity to the memory devices themselves.
Solution Approach 2:
The controller implements periodic switching between multiple memory devices during write operations. Instead of writing continuously to a single device until completion, the controller alternates write commands between multiple devices in a periodic manner, ensuring that while one device is in cache-busy or programming state, another device is ready to receive data, thus reducing overall idle time on the interface.
2Productivity
If the controller waits for memory device readiness verification, then data integrity is ensured, but write throughput is reduced due to waiting time
Solution Approach 1:
The controller performs preliminary verification of memory device readiness using predicted programming completion times before issuing write commands. By anticipating which devices will be ready next based on their current operation status and predicted completion times, the controller can prepare and queue write commands in advance, ensuring reliability through verification while minimizing waiting time that would otherwise reduce throughput.
3Productivity
If the controller optimizes write scheduling to reduce idle periods, then write throughput improves, but control complexity increases
Solution Approach 1:
The controller calculates predicted programming completion times for multiple memory devices in advance and uses these predictions to optimize the write schedule. By performing this prediction and scheduling preparation beforehand, the controller reduces the need for complex real-time decision-making during write operations, thereby improving throughput while keeping the actual execution logic relatively simple and manageable.
4Productivity
If sequential writing to single memory device is used, then interface simplicity is maintained, but programming inefficiency increases due to cache-busy periods
Solution Approach 1:
The controller implements periodic switching between multiple memory devices during write operations. By alternating write commands between multiple devices in a systematic periodic manner, the controller ensures that interface idle time during cache-busy and programming periods is minimized, thereby improving throughput. The periodic nature of the switching provides a structured, manageable scheduling approach that balances performance improvement with controlled complexity.
Data Source
AI summary
A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.