Storage Controller Selective Memory State Determination

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Solution Overview

Problem

Data storage devices face challenges in quickly recovering from abnormal power-offs, particularly in determining the state of memory units and performing garbage collection operations efficiently after power restoration, which affects data integrity and system boot time.

Innovation Solution

A data storage device with a controller that performs state determination operations in a specific sequence, skipping certain memory units based on mapping update status, and conducts garbage collection based on the results to ensure quick recovery and data validity assessment.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If state determination operation is performed to all memory units after abnormal power-off, then data integrity is ensured, but system boot time increases

Engineering Contradiction:
Improvedata integrityVSAvoidsystem boot time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The memory units are segmented into three categories based on write sequence position relative to error-correction-failed data: first memory units (before the failed unit) require full state determination, second memory units (after the failed unit) can be skipped, and third memory units (after pointed memory unit) require state determination. This segmentation allows selective processing that maintains data integrity for critical units while reducing overall boot time.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Instead of performing state determination on all memory units (excessive action), the patent applies partial action by selectively determining states only for first and third memory units while skipping second memory units. This partial approach is sufficient to ensure data integrity while significantly reducing the time required during system boot.

Inventive Principle:
Principle #16Partial or excessive action

2Loss of time

If state determination operation is skipped for certain memory units, then system boot time is reduced, but data integrity may be compromised

Engineering Contradiction:
Improvesystem boot timeVSAvoiddata integrity
Core Design Contradiction:
Loss of timeVSReliability

Solution Approach 1:

Different quality of state determination is applied to different regions of memory units. First memory units receive full state determination with error correction to ensure high data integrity. Second memory units are skipped to reduce time. Third memory units receive state determination to maintain integrity. This local differentiation optimizes both time and reliability.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system performs preliminary error correction on read data before state determination. This preliminary action ensures that even when skipping certain memory units, the data integrity of processed units is maintained through pre-validation, reducing the need for exhaustive checking of all units.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If garbage collection operation is performed on all memory units, then data validity is ensured, but operational overhead increases

Engineering Contradiction:
Improvedata validityVSAvoidoperational overhead
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Garbage collection is segmented based on state determination results. Only memory units that require state determination (first and third units) are subjected to garbage collection. This segmentation ensures data validity for units that need it while reducing operational overhead by excluding units where state is already known or skipping is safe.

Inventive Principle:
Principle #1Segmentation

4Reliability

If error correction is performed on all read data, then data integrity is maximized, but processing time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

Error correction is applied partially rather than universally. It is performed on read data from first memory units and third memory units where state determination is required, but skipped for second memory units. This partial application maintains data integrity where necessary while reducing overall processing time during system boot.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10083114B2Data storage device and operating method thereof
Publication Date: 2018.09.25 MIMIRIP LLC
  • US10083114B2 patent drawing
  • US10083114B2 patent drawing
  • US10083114B2 patent drawing

AI summary

A data storage device includes a storage medium including a plurality of memory units; and a controller suitable for performing a state determination operation to first memory units in order of a write sequence until a memory unit stored with an error-correction-failed data when a power supply is restored after an abnormal power-off, skipping the state determination operation to second memory units between the memory unit storing the error-correction-failed data and a pointed memory unit, performing the state determination operation to third memory units after the pointed memory unit in order of the write sequence, and performing a garbage collection operation to the first to third memory units based on a result of the state determination operation.