Controller Allocating SLC Turbo Write Planes
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Solution Overview
Problem
Existing memory systems face challenges in efficiently handling mixed turbo write and normal write requests, which can degrade the performance of turbo write operations due to the need to wait for completion of normal write requests, leading to suboptimal write performance and potential memory block wear issues.
Innovation Solution
A controller is designed to allocate separate memory planes for turbo write and normal write operations, utilizing single level cell (SLC) mode for high-speed turbo write requests and multi-level cell (MLC) mode for normal write requests, allowing concurrent processing and prioritizing turbo write requests without waiting for normal write completion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the memory system processes normal write requests before turbo write requests, then normal write operations can complete properly, but turbo write performance deteriorates due to waiting delays
Solution Approach 1:
The memory system is segmented into distinct plane groups: first plane groups dedicated to turbo write operations and second plane groups dedicated to normal write operations. This segmentation allows independent processing of different write types without mutual interference, resolving the contradiction between ensuring normal write completion and maintaining turbo write speed.
Solution Approach 2:
The system introduces a dimensional separation by organizing memory planes into different groups that operate independently. Instead of sequential processing in a single dimension, the system processes turbo writes and normal writes in parallel across different plane group dimensions, eliminating waiting delays while ensuring both operation types complete properly.
2Device complexity
If the memory system uses a single plane for both turbo write and normal write operations, then device complexity is reduced, but write performance deteriorates due to operation conflicts
Solution Approach 1:
The memory planes are segmented into first plane groups for turbo writes and second plane groups for normal writes. This segmentation resolves operation conflicts by dedicating specific planes to specific operation types, thereby maintaining high write performance without excessively increasing device complexity through a systematic allocation structure.
Solution Approach 2:
Different plane groups are assigned different operational characteristics: first plane groups are optimized for high-speed turbo writes while second plane groups handle standard normal writes. This local quality differentiation allows each plane group to excel at its designated function, improving overall write performance without requiring complete system redesign.
3Productivity
If the memory system processes mixed turbo write and normal write requests concurrently without separation, then resource utilization improves, but turbo write performance deteriorates due to interference from normal writes
Solution Approach 1:
By segmenting planes into dedicated groups, the system maintains high resource utilization through parallel processing while preventing interference between operation types. First plane groups process turbo writes exclusively while second plane groups process normal writes, ensuring turbo write performance is guaranteed without being degraded by normal write operations.
Data Source
AI summary
A controller configured to control memory chips in communication with the controller is provided. The controller comprises: a host interface configured to receive a request from a host; an address mapper configured to, upon receipt of both a turbo write request for writing data to one or more high-speed storage blocks at a high speed to and a normal write request for writing data to one or more storage blocks at a lower speed, allocate a first plane including a memory block configured to perform write operations in a single level cell mode at the high speed to a first plane group in order to respond to the turbo write request, and allocate a second plane to a second plane group at the slower speed in order to respond to the normal write request; and a memory interface configured to control the memory chips.