Controller Synchronization via Memory Modification Tracking
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Solution Overview
Problem
Industrial control systems face challenges in synchronizing primary and redundant controllers without disrupting the controlled process, especially due to the large and continuously changing I/O data table, which is difficult to transmit using custom processors and integrated circuits, and the increasing use of commercially available microprocessors that lack the same functionality.
Innovation Solution
The use of a memory management unit to designate a portion of memory as read-only, trapping write instructions, logging modified locations, and communicating these changes between controllers, allowing for efficient synchronization of primary and redundant controllers using commercially available hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If custom processors and integrated circuits (ASIC) are used to monitor and flag changes in the I/O data table, then synchronization between primary and redundant controllers is achieved, but device complexity and cost increase
Solution Approach 1:
The patent replaces custom hardware circuitry (ASIC) with a software-based solution running on commercially available microprocessors. The memory management unit and abort handler mechanisms substitute for dedicated synchronization hardware, achieving the same reliability through software control rather than custom electronic circuits.
Solution Approach 2:
The patent makes commercially available microprocessors perform the specialized synchronization function that previously required custom ASICs. By using universal components for both general control and synchronization tasks, the system reduces complexity while maintaining reliability through the memory protection and abort handling mechanisms.
2Reliability
If the entire I/O data table is transmitted to the redundant controller, then complete synchronization is achieved, but transmission time and system disruption increase
Solution Approach 1:
The patent extracts only the modified portions of the I/O data table for transmission to the redundant controller, rather than transmitting the entire table. The abort handler identifies specific modified memory locations, and only these extracted changes are communicated, significantly reducing transmission time while maintaining complete synchronization of all necessary data.
Solution Approach 2:
The patent segments the I/O data table transmission into individual modified locations or small groups of modifications rather than transmitting the complete table at once. This segmentation allows the redundant controller to receive updates incrementally, reducing the time the primary controller is blocked and minimizing system disruption.
3Ease of manufacture
If commercially available microprocessors are used instead of custom processors, then cost and flexibility are improved, but functionality and synchronization capability are reduced
Solution Approach 1:
The patent changes the operational parameters of commercially available microprocessors by implementing specific software mechanisms (memory management unit with read-only designation, abort handlers, and modification logging). These parameter changes in software behavior enable the standard processors to achieve synchronization functionality previously requiring custom hardware, maintaining adaptability while reducing cost.
Data Source
AI summary
A method for identifying memory modifications includes designating a first portion of a first memory as read-only. An abort condition is identified responsive to receiving a write instruction having a target address within the first portion. In response to the abort condition, a second portion of the first memory including at least the target address is flagged as being modified. The write instruction is executed.