Controller Tapped Delay Optimization for Semiconductor Memory Write Training
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Solution Overview
Problem
Current semiconductor memory devices face challenges in enhancing write training speed, particularly in determining optimal tapped delays for successful write operations, which affects the efficiency and speed of data storage and retrieval.
Innovation Solution
A controller method that determines the minimum and maximum pass tapped delays by adjusting offsets and applying these delays to write operations, optimizing the tapped delay for each memory chip to ensure successful data transfer, thereby enhancing write training speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional write training methods are used to determine optimal tapped delays, then write operation reliability is improved, but write training time increases
Solution Approach 1:
The patent applies preliminary action by pre-determining the minimum and maximum pass tapped delays through offset-based calculations before actual write operations begin. The controller performs offset storage and tapped delay storage in advance, establishing the optimal tapped delay range beforehand, which eliminates the need for time-consuming iterative training during normal operation.
Solution Approach 2:
The system uses self-service by automatically determining optimal tapped delays through internal offset calculations and stored values. The controller independently computes minimum and maximum pass tapped delays using pre-stored offsets without requiring external calibration or manual intervention, enabling rapid adaptation to different memory devices.
2Measurement precision
If multiple memory chips share a channel and individual training is performed for each chip, then write operation accuracy is improved, but overall productivity decreases
Solution Approach 1:
The patent implements universality by creating a shared offset storage and tapped delay storage that serves all memory chips on the channel. The controller determines minimum and maximum pass tapped delays that are applicable across multiple chips, allowing a single training process to benefit all chips rather than requiring separate training for each device.
Solution Approach 2:
The system merges the training processes of multiple memory chips by using common offset values and tapped delay parameters. Instead of performing individual training sequences for each chip, the controller combines the training into a unified process where determined offsets and delays are applied channel-wide, significantly improving throughput.
Data Source
AI summary
Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay.