Programmable Controller Synchronization via Temporary Memory Buffering

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Solution Overview

Problem

Existing programmable controllers face challenges in preventing failures during the synchronization process of device data without requiring a ladder program for correction.

Innovation Solution

A programmable controller with a temporary memory, working memory, and control unit that periodically transmits request packets to external devices, acquires data from response packets, and writes it into the working memory only when all response packets are received within a control period, ensuring synchronized data reflection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the programmable controller uses traditional synchronization control methods, then device data can be collected, but synchronization failures occur when response packets are not received within the control period

Engineering Contradiction:
Improvesynchronization reliabilityVSAvoidcontrol program complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a temporary memory as an intermediary storage between the response packets reception and the working memory writing. This temporary memory holds device data temporarily, allowing the system to wait for all response packets without immediately writing to working memory, thus preventing synchronization failures while maintaining simple control logic

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs preliminary storage of device data in temporary memory before the final writing to working memory. By storing data in temporary memory first during the control period, the system prepares all necessary data in advance, then writes to working memory only when all response packets are received, ensuring synchronization without complex correction programs

Inventive Principle:
Principle #10Preliminary action

2Productivity

If the controller writes device data to working memory continuously, then data availability is improved, but synchronization accuracy deteriorates due to potential data inconsistencies

Engineering Contradiction:
Improvedata processing efficiencyVSAvoidsynchronization precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The patent performs preliminary storage of device data in temporary memory during the control period, preparing all data in advance. This preliminary action allows the system to have data ready without writing to working memory until synchronization is complete, thus maintaining both efficiency and precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the memory into two distinct parts: temporary memory for intermediate storage and working memory for final synchronized data. This segmentation allows the system to maintain data in a preparatory state without committing to the final working memory until all synchronization conditions are met, preserving both productivity and precision

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS10416644B2Programmable controller and synchronization control program
Publication Date: 2019.09.17 MITSUBISHI ELECTRIC CORP
  • US10416644B2 patent drawing
  • US10416644B2 patent drawing
  • US10416644B2 patent drawing

AI summary

A programmable controller periodically controls a plurality of external devices. The programmable controller includes a temporary memory, a working memory, and a control unit. The control unit transmits request packets to each of the external devices, the request packets requesting transmission of device data to be used in control of the external devices, the external devices being targets to be subjected to synchronization control, acquires the device data from response packets received from the external devices in response to the request packets, and stores the acquired device data into the temporary memory, and writes the device data stored in the temporary memory into the working memory on the condition that the respective response packets in response to the request packets transmitted within the same control period are received from the external devices.