Memory Controller Two-Level Wear-Leveling for Hot Data
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Solution Overview
Problem
Current wear-leveling algorithms in memory systems do not account for the different types of data (hot, warm, or cold) written by the host, leading to uneven distribution of program/erase cycles across memory blocks, which reduces the endurance of storage products.
Innovation Solution
A two-level wear-leveling scheme is introduced that utilizes write counts at block and codeword levels to manage data swaps more precisely, using L2P mapping tables and swap bitmaps to evenly distribute write operations based on the hotness of host data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional wear-leveling algorithms are used without considering data types, then the implementation is simple, but the endurance of storage products is reduced due to uneven distribution of program/erase cycles
Solution Approach 1:
The patent applies local quality by differentiating wear-leveling strategies based on data types (hot, warm, cold). Different memory blocks are assigned different wear-leveling treatments according to the access patterns of their stored data, rather than applying a uniform approach. This allows the system to optimize endurance for frequently accessed data while maintaining simplicity for less accessed data.
Solution Approach 2:
The patent implements dynamic wear-leveling that adapts to changing data access patterns. The system continuously monitors data types and adjusts wear-leveling operations accordingly, transitioning between different wear-leveling modes based on observed access patterns. This dynamic approach allows the algorithm to respond to changing workloads while maintaining reasonable complexity.
2Reliability
If wear-leveling operations are performed frequently to balance program/erase cycles, then the distribution of writes becomes more uniform, but the loss of time increases due to additional wear-leveling operations
Solution Approach 1:
The patent applies partial action by performing wear-leveling operations selectively rather than continuously. The system performs wear-leveling only when necessary, based on the accumulation of write operations and the identification of data types that require balancing. This reduces the total number of wear-leveling operations while still achieving adequate distribution uniformity.
Solution Approach 2:
The patent implements periodic wear-leveling operations that are triggered by specific conditions such as reaching a threshold number of writes or detecting changes in data access patterns. Rather than continuous wear-leveling, the system periodically performs balancing operations, which reduces time loss while maintaining acceptable uniformity of program/erase cycle distribution.
3Measurement precision
If fine-grained wear-leveling at codeword level is implemented, then the precision of wear distribution improves, but the device complexity increases due to additional monitoring and swapping operations
Solution Approach 1:
The patent applies segmentation by dividing the memory into different levels (block level and codeword level) and applying appropriate wear-leveling strategies at each level. The block-level wear-leveling provides coarse-grained management, while codeword-level operations provide fine-grained precision only where needed. This hierarchical segmentation reduces overall complexity compared to pure codeword-level management.
Solution Approach 2:
The patent performs preliminary wear-leveling at the block level before conducting more精细 operations at the codeword level. By first balancing wear at the coarser block level, the system reduces the amount of subsequent codeword-level intervention needed, thereby reducing the complexity of monitoring and swapping operations while maintaining precision where it matters most.
Data Source
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AI summary
In certain aspects, a memory system includes a non-volatile memory device and a memory controller coupled to the non-volatile memory device. The non-volatile memory device includes a plurality of memory groups. Each of the memory groups includes a plurality of memory units. The memory controller is configured to perform at least one of a first wear-leveling process by swapping a first memory group of the memory groups and a second memory group of the memory groups based on a first group write count for the first memory group and a second group write count for the second memory group, or a second wear-leveling process by swapping a first memory unit of the memory units and a second memory unit of the memory units based on a first unit write count for the first memory unit and a second unit write count for the second memory unit.