Converged Memory Device Segmentation for Power-Speed Trade-off
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current data centers face challenges in efficiently processing and managing large-scale data due to limitations in resource allocation and power consumption, particularly in supporting high-data-rate applications like AI, autonomous driving, and virtual reality, where legacy data centers are not optimized for modular and flexible resource restructuring.
Innovation Solution
A converged memory device with a controller that dynamically allocates DRAMs into fast and normal memory cells based on request requirements, using switching devices to couple or decouple memory cells from sense amplifiers, optimizing data processing rates and power consumption by classifying memory cells into near and far segments with asymmetrical bit line structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If all memory cells are coupled to sense amplifiers for normal data processing, then data processing rate is adequate, but power consumption increases
Solution Approach 1:
The cell matrix is divided into two distinct regions: first region memory cells coupled to sense amplifiers and second region memory cells decoupled from sense amplifiers. This segmentation allows the system to process only the necessary portion of data at high speed while leaving other data in low-power standby mode, thereby reducing overall power consumption without completely sacrificing data processing capability.
Solution Approach 2:
The system dynamically switches between coupling and decoupling memory cell regions based on data processing requirements. When fast data processing is needed, the controller activates the switching device to couple first region memory cells to sense amplifiers; when power saving is prioritized, the switching device decouples these regions. This dynamic adaptation resolves the contradiction between continuous high performance and energy efficiency.
2Use of energy by moving object
If second region memory cells are decoupled from sense amplifiers, then power consumption decreases, but data processing rate for those cells reduces
Solution Approach 1:
Different regions of the cell matrix are assigned different operational qualities: first region memory cells maintain full coupling to sense amplifiers for high-speed access when needed, while second region memory cells operate in a decoupled low-power state. This local differentiation allows the system to optimize power consumption in specific regions without compromising the performance of other regions that may require high-speed processing.
3Speed
If memory cells are positioned closer to sense amplifiers, then data processing rate improves, but device area increases
Solution Approach 1:
The cell matrix is segmented into first and second regions with different spatial relationships to sense amplifiers. First region memory cells are positioned closer to sense amplifiers to enable fast data processing, while second region memory cells are positioned farther away. This segmentation allows the system to achieve high-speed processing for critical data without requiring all memory cells to be positioned close to sense amplifiers, thereby controlling overall device area.
Solution Approach 2:
The patent employs an asymmetrical bit line structure where bit lines have different lengths depending on their connection to first or second region memory cells. This asymmetrical design optimizes the electrical characteristics for fast access in the first region while accepting longer bit line lengths in the second region, resolving the contradiction between speed optimization and area constraints through intentional asymmetrical positioning.
Data Source
AI summary
A converged memory device includes at least a first memory and a second memory and a controller to select the first or second memory for performing fast or normal data processing, respectively, in response to a request from a host. The first memory includes a sense amplifier, one or more cell matrices, and a switching device. The cell matrices includes one or more first region memory cells disposed less than a first distance from the sense amplifier and one or more second region memory cells disposed more than a second distance from the sense amplifier, the second distance being longer than the first distance. The switching device is disposed between the first and second region memory cells. The controller controls the switching device to couple the first region memory cells to the sense amplifier and to decouple the second region memory cells from the sense amplifier according to the request.