Convergent Fin and Nanostructure Transistors for Tighter Cell Spacing
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Solution Overview
Problem
The semiconductor integrated circuit (IC) industry faces challenges in scaling down due to layout restrictions on spacing between gate isolation structures and neighboring semiconductor fins, which constrain cell height scaling and increase processing complexity.
Innovation Solution
A fabrication process is employed to form FinFETs and GAAFETs in a single IC cell, utilizing a double-patterning or multi-patterning process to create smaller pitches and improve spacing constraints, combining p-type FinFETs and n-type GAAFETs for enhanced performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-patterning process is used, then manufacturing process is simple, but spacing between gate isolation structures and fins is large, constraining cell height scaling
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning or multi-patterning. First, mandrels are formed and then removed, followed by formation of fins and gate isolation structures in separate steps. This segmentation enables smaller pitch and improved spacing constraints that would not be achievable with single-patterning, directly resolving the contradiction between manufacturing precision and process complexity.
Solution Approach 2:
The patent employs preliminary action by forming mandrels first as temporary structures that define the pitch before the actual fin and gate isolation structure formation. The mandrels are removed after serving their patterning purpose, allowing subsequent structures to be formed with precise spacing. This preliminary structuring enables the achieving of smaller pitches and improved spacing constraints.
2Productivity
If cell height scaling is increased, then functional density increases, but spacing constraints between gate isolation structures and fins become more difficult to meet
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar spacing constraints to vertical stacking. Multiple fins and gate isolation structures are arranged in a converged configuration where spacing is optimized in the lateral direction while utilizing vertical height for increased functional density. This allows functional density to increase without compromising the required spacing between structures.
Solution Approach 2:
The patent merges FinFET and gate-all-around FET structures into a convergent configuration within the same cell. This merging allows shared use of gate isolation structures and optimized spacing arrangements, enabling increased functional density while maintaining manufacturing precision for spacing constraints through the unified structure design.
3Manufacturing precision
If double-patterning or multi-patterning process is used, then smaller pitches and improved spacing are achieved, but manufacturing process complexity increases
Solution Approach 1:
The patent segments the manufacturing process into distinct modular stages: mandrel formation, mandrel removal, fin formation, and gate isolation structure formation. Each stage can be independently optimized and controlled, making the complex double-patterning or multi-patterning process more manageable while achieving smaller pitches and improved spacing precision.
Data Source
AI summary
A device includes a substrate, a first semiconductor fin over the substrate extending in a first lateral direction, a first vertical stack of semiconductor nanosheets over the substrate extending in the first lateral direction, and an inactive fin between the first semiconductor fin and the first vertical stack extending in the first lateral direction. A first gate structure surrounds and covers the first semiconductor fin, and extends in a second lateral direction substantially perpendicular to the first lateral direction. A second gate structure surrounds and covers the first vertical stack, and extends in the second lateral direction.