Convergent Rounding Pattern Detector for DSP Fabric Bottlenecks
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Solution Overview
Problem
The increasing demand for real-time, concurrent arithmetic operations in digital signal processing applications, such as in 3G base stations, is not adequately met by traditional DSP chips or Programmable Logic Devices (PLDs) due to bottlenecks in the PLD fabric, necessitating a more efficient digital signal processing solution.
Innovation Solution
An integrated circuit (IC) with a pattern detector circuit for convergent rounding, featuring an adder circuit, comparison circuit, and rounding circuitry, which includes a multiplier circuit to produce a product, and a method involving multiplication, addition, bitwise comparison, and convergent rounding based on a comparison bit, to enhance DSP performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple DSP elements are configured in PLD fabric to allow concurrent DSP operations, then the quantity of arithmetic operations is improved, but the fabric becomes a bottleneck limiting further performance improvement
Solution Approach 1:
The patent divides the DSP processing function into separate, dedicated hardware modules (multiplier circuits, adder circuits, pattern detector circuits) that operate independently and in parallel. This segmentation eliminates the fabric bottleneck by removing the need for complex programmable interconnect, as each module has dedicated pathways for data flow.
Solution Approach 2:
The patent introduces dedicated interconnect structures that directly connect multiplier circuits to adder circuits and pattern detector circuits, serving as intermediaries that bypass the PLD fabric. This dedicated interconnect methodology eliminates the fabric bottleneck by providing direct, high-speed data pathways between processing modules.
2Adaptability or versatility
If traditional DSP chips or PLDs are used to meet increasing demand for real-time arithmetic operations, then programmability is maintained, but performance is inadequate due to fabric bottlenecks
Solution Approach 1:
The patent combines static dedicated hardware modules with dynamic programmable elements. The multiplier circuits, adder circuits, and pattern detector circuits are implemented as fixed-function modules for high-speed operation, while selectability and configuration are achieved through programmable multiplexers and control logic, allowing the system to adapt to different algorithms while maintaining high performance.
3Measurement precision
If convergent rounding is implemented using traditional methods, then rounding functionality is achieved, but the comparison and masking operations increase circuit complexity
Solution Approach 1:
The patent performs preliminary bitwise comparison between the summation result and a pattern value, and applies masking based on control signals before the final rounding decision. This preliminary action simplifies the main comparison circuit by pre-processing the data, eliminating the need for complex multi-stage comparison logic.
Data Source
AI summary
An integrated circuit (IC) for convergent rounding including: an adder circuit configured to produce a summation; a comparison circuit configured to bitwise compare the summation with an input pattern, bitwise mask the comparison using a mask, and combine the masked comparison to produce a comparison bit; and rounding circuitry for rounding the summation based at least in part on the comparison bit.