Conversion Circuitry for Signed Digit to Unsigned Conversion
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Solution Overview
Problem
Existing data processing technologies face inefficiencies in converting redundant to non-redundant representations, particularly when dealing with negative numbers, as previous algorithms introduce latency and require additional circuitry, leading to increased power consumption and space usage.
Innovation Solution
A data processing apparatus and method that performs on-the-fly conversion of signed digits to unsigned digits, using conversion circuitry to generate unsigned digits based on the signed digit's value and concatenating them with intermediate data, allowing for speculative generation of candidate unsigned digits to reduce latency and eliminate the need for addition circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conversion is performed on the fly for each digit as it is received, then processing speed is improved, but the algorithm does not work when the overall number being output is negative
Solution Approach 1:
The patent inverts the conventional approach by performing negative-output conversion during the iterative process rather than waiting for all digits to be received. Instead of converting to positive numbers and inverting at the end, the conversion circuitry directly generates negative output values by selecting appropriate unsigned digit candidates based on the sign bit, enabling on-the-fly conversion for negative numbers.
Solution Approach 2:
The patent performs preliminary conversion actions during each iteration by pre-selecting candidate unsigned digits that correspond to possible signed digit values. The conversion circuitry prepares potential output values in advance based on the current signed digit and previous intermediate data, allowing immediate output without waiting for the complete number to be received.
2Adaptability or versatility
If all digits are received before conversion, then negative numbers can be handled, but latency is introduced
Solution Approach 1:
The patent maintains continuous conversion action during the entire iterative process. The conversion circuitry operates continuously alongside the digit generation, converting signed digits to unsigned digits on-the-fly without interruption or waiting periods. This eliminates the idle time that would occur if conversion waited for all digits to be received before starting.
3Object-generated harmful factors
If inversion is performed for negative numbers after conversion, then negative output is achieved, but additional addition circuitry is required which increases space and power consumption
Solution Approach 1:
The patent extracts the inversion operation from the conversion process. Instead of performing addition and inversion as separate post-processing steps, the conversion circuitry directly generates the negative output value by selecting appropriate unsigned digit candidates during the conversion itself. This removes the need for separate inversion circuitry and its associated power consumption.
Solution Approach 2:
The patent merges the sign handling into the conversion process itself. The sign bit of the output number is used to select between positive and negative candidate unsigned digits during conversion, combining what would traditionally be separate operations (conversion and sign inversion) into a single integrated process that reduces circuit complexity.
Data Source
AI summary
A data processing apparatus is provided to convert a plurality of signed digits to an output value, the data processing apparatus comprising: receiver circuitry to receive, at each of a plurality of iterations, a signed digit from the plurality of signed digits, and previous intermediate data. Conversion circuitry performs a negative-output conversion from the signed digit to an unsigned digit, such that the output value comprising the unsigned digit is negative. Concatenation circuitry concatenate bits of the unsigned digit and bits of the previous intermediate data to produce updated intermediate data and output circuitry provides the updated intermediate data as the previous intermediate data of a next iteration. After the plurality of iterations, the output circuitry outputs at least part of the updated intermediate data as the output value.