Conversion Lookaside Buffer for Code Cache Translation

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Solution Overview

Problem

Current code transformation processes in digital computer systems, such as translation and emulation, incur significant overhead due to processor cycles, leading to performance penalties and latency issues, especially during startup and memory management.

Innovation Solution

A hardware-based acceleration method for converting guest instructions to native instructions using a conversion look aside buffer that stores mappings between guest and native addresses, allowing for rapid execution and reduced memory trips by pre-fetching and caching frequently used blocks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If software-based translation or emulation is used to enable non-native instructions to execute on native hardware, then compatibility and functionality are improved, but processor overhead and performance penalty increase significantly

Engineering Contradiction:

ImprovecompatibilityVSAvoidperformance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent replaces software-based translation mechanisms with a hardware translation layer implemented as specialized circuitry. This hardware layer directly translates non-native instructions to native instructions in parallel with the main processor operation, eliminating the sequential software interpretation overhead while maintaining instruction compatibility across different architectures

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces a hardware translation layer as an intermediary between the non-native instruction set and the native processor. This intermediary translates instructions in real-time during execution, allowing non-native code to run on native hardware without the performance penalty of software-based translation or emulation

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If JIT compilation is used to optimize translated code, then execution performance of translated code is improved, but startup delay and memory management overhead increase

Engineering Contradiction:

Improveexecution performanceVSAvoidstartup delay

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent pre-translates instruction sequences to native code and caches the translated versions in a dedicated translation cache before execution is needed. When non-native code is encountered, the hardware translation layer checks the cache for previously translated sequences, allowing frequently executed code to run directly from the cache without repeated translation overhead or JIT compilation delays

Inventive Principle:

Principle #10Preliminary action

3Device complexity

If interpretation mode is used for code transformation, then processor overhead per translation is reduced, but execution performance of translated code deteriorates

Engineering Contradiction:

Improvetranslation overheadVSAvoidexecution performance

Core Design Contradiction:

Device complexityVSProductivity

Solution Approach 1:

The patent replaces software interpretation with hardware-based parallel translation. The hardware translation layer operates concurrently with the main processor, translating multiple non-native instructions to native instructions in parallel rather than sequentially interpreting them, thereby achieving both low overhead and high execution performance

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

4Adaptability or versatility

If frequent memory trips are required for code transformation and management, then translation flexibility is improved, but latency penalty increases

Engineering Contradiction:

Improvetranslation flexibilityVSAvoidlatency

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent implements a hierarchical caching structure where recently translated instruction sequences are stored in a fast translation cache nested within the processor architecture. This nested cache structure allows the system to retain translation flexibility while minimizing trips to main memory, as the hardware translation layer can directly access and reuse translated code from the nested cache without external memory access

Inventive Principle:

Principle #7Nested doll (Nesting)

Data Source

PatentUS10241795B2Guest to native block address mappings and management of native code storage

Publication Date: 2019.03.26 INTEL CORP

AI summary

A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.