Switching Converter Synchronous Rectifier Delay Lock Loop

The patent applies preliminary action by predicting the turn-on time of the primary side switch in advance and compensating for the delay time of the synchronous rectifier turn-off operation. The delay locked loop generates a control signal that anticipates the timing conflict, ensuring the synchronous rectifier turns off before the primary side switch turns on, thus preventing overlap while maintaining high efficiency.

The patent implements feedback through a delay locked loop that continuously monitors the timing relationship between the primary side switch and synchronous rectifier. The feedback mechanism adjusts the synchronous rectifier turn-off timing based on the detected delay, ensuring optimal performance while preventing harmful overlap, thus maintaining both efficiency and stability.

The patent replaces the traditional hard switching mechanical operation with a synchronized switching mechanism controlled by the delay locked loop. This substitution eliminates the large voltage-current crossing losses of hard switching while maintaining circuit simplicity, achieving low power loss through timing-controlled switching rather than forceful commutation.

The patent changes the switching parameters by using a delay locked loop to precisely control the timing of the synchronous rectifier turn-off. This parameter control approach achieves low switching loss without the large voltage and current stresses of resonant schemes, while maintaining good control properties through deterministic timing rather than relying on resonant waveforms.