Galvanic Isolation Jitter Correction in Power Converter Circuit Assemblies
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Solution Overview
Problem
Existing circuit arrangements for converters experience significant jitter in digital switching signals due to the use of optocouplers, leading to broadband noise and reduced positioning accuracy in control systems, especially when handling high voltages and frequencies.
Innovation Solution
A circuit arrangement that employs a high-frequency digital isolator for clock signals and a correction circuit to synchronize PWM signals with minimal jitter, using a clock edge-controlled D flip-flop to prevent interference, thereby reducing noise and ensuring precise control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If optocouplers are used for galvanic isolation of PWM signals, then galvanic isolation is achieved, but jitter increases significantly
Solution Approach 1:
The patent segments the isolation function into two separate channels: one for PWM signals using optocouplers and another for clock signals using low-jitter isolators. This segmentation allows each channel to be optimized for its specific function, with the clock channel providing high-precision timing reference that compensates for jitter in the PWM channel.
Solution Approach 2:
The patent introduces a clock signal as an intermediary reference that mediates between the isolated PWM signal and the control system. The clock signal passes through a separate low-jitter isolator and serves as a timing reference to resynchronize the PWM edges, effectively transferring precise timing information across the galvanic isolation barrier without directly transmitting the PWM signal itself.
2Reliability
If optocouplers are used for galvanic isolation of clock signals, then galvanic isolation is achieved, but jitter is introduced
Solution Approach 1:
The patent applies different quality requirements to different signal paths: high-precision low-jitter isolators are used specifically for the clock signal path where timing accuracy is critical, while standard optocouplers are sufficient for PWM signals where absolute timing is less critical. This local differentiation of quality ensures timing precision is maintained where needed without unnecessarily increasing system complexity.
3Measurement precision
If separate transmission of PWM and clock signals is used, then jitter can be reduced, but device complexity increases
Solution Approach 1:
The patent merges the PWM signal path and clock signal path at the output side, where the resynchronized PWM signal (aligned to the clock edges) is combined with the clock signal to drive the power transistors. This merging approach allows the benefits of separate transmission (reduced jitter) to be achieved while maintaining a relatively simple overall architecture that leverages existing isolated bus structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces jitter by a factor of ten, improving positioning accuracy and preventing interference-related issues, enabling precise and low-noise control of electric drives.
Implementation Method 1
a first isolator (Si) for galvanically isolated transmission of the PWM signal (G) into a high-voltage area of the inverter
Implementation Method 2
a second isolator (Ci) for galvanically isolated transmission of the clock signal (CLK) with a jitter that is at least two times lower than that of the first isolator
Implementation Method 3
a correction circuit (DFF) that corrects jitter of the galvanically isolated PWM signal on the basis of the galvanically isolated clock signal
Data Source
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AI summary
A circuit arrangement for controlling power transistors (T1, T2) of an inverter is disclosed, comprising a logic circuit (DSP) for generating a PWM signal (G) and a clock generator (C) for generating a clock signal (CLK), as well as a first or second insulator (Si, Ci) for galvanically isolated transmission of the PWM signal (G) or the clock signal (CLK) into a high-voltage area (HV) of the inverter, resulting in a galvanically isolated PWM signal (Giso) and a galvanically isolated clock signal (CLKiso).The circuit arrangement also includes a correction circuit (DFF) that corrects jitter of the galvanically isolated PWM signal (Giso) on the basis of the galvanically isolated clock signal (CLKiso), characterized in that the first insulator (Si) for the PWM signal (G) is designed to transmit both DC and AC voltage signals, and that the second insulator (Ci) for galvanically isolated transmission has a jitter that is at least two times lower, preferably ten times lower, and particularly preferably twenty times lower than that of the first insulator (Si).