Signal Converter Metastability Detection for Bit Error Reduction
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Solution Overview
Problem
Pipelined converter systems experience bit error rate degradation due to analog input signals near reference thresholds causing comparator metastability, which delays or prohibits decision generation and results in conversion errors.
Innovation Solution
The system configures comparator failure sensing and substitution of predetermined digital codes when decisions are outside a predetermined digital code window, and incorporates metastability detectors to reduce errors by ensuring timely residue generation and alignment of digital bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If pipelined converter systems use flash converters with latch converters to achieve high conversion speed, then conversion speed is improved, but bit error rate degrades due to comparator metastability
Solution Approach 1:
The patent applies preliminary action by detecting comparator metastability conditions before they cause conversion errors. The system monitors comparator outputs during the regeneration mode and identifies when comparators are in metastable states, allowing corrective action to be taken before the error propagates through the pipelined converter stages.
Solution Approach 2:
The patent introduces an intermediary mechanism - a detection and correction system that acts as a mediator between the flash converter comparators and the subsequent processing stages. This intermediary detects metastability conditions and substitutes corrected digital codes, preventing the propagation of errors while maintaining the high-speed operation of the flash converters.
2Measurement precision
If analog input signals are near reference thresholds, then conversion precision is maintained, but comparator metastability occurs causing decision delays
Solution Approach 1:
The patent implements feedback by continuously monitoring comparator outputs to detect metastability conditions. When a comparator is detected to be in a metastable state (indicated by neither valid logic state being asserted), the system triggers a correction mechanism that substitutes a predetermined digital code, thereby compensating for the decision delay without sacrificing conversion precision.
Solution Approach 2:
The patent applies parameter changes by altering the digital code output when metastability is detected. Instead of waiting for the metastable comparator to resolve (which would cause time loss), the system changes the output parameter to a predetermined code that maintains precision while avoiding the time penalty of metastability resolution.
3Measurement precision
If pipelined converter systems process multiple conversion stages to obtain all conversion bits, then conversion accuracy is improved, but system complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the conversion process into distinct stages (flash converter stage, detection stage, correction stage). Each stage has a specific function, and the overall system achieves high accuracy through this segmented approach. The metastability detection and correction mechanism is segmented as a separate functional block that monitors and corrects errors without interfering with the primary conversion process.
Solution Approach 2:
The patent introduces an intermediary detection and correction system that manages the complexity of multiple conversion stages. This intermediary layer coordinates between the flash converters and subsequent processing, handling error correction centrally rather than requiring complex error management in each individual stage, thereby reducing overall system complexity while maintaining accuracy.
Data Source
AI summary
Signal converter systems are provided which reduce degradation of system bit error rate that is caused by metastable conversion errors which generally occur when analog input signals are near reference thresholds Vth of system comparators. When operating correctly, the comparators generate a corresponding converter code when the input signals cross the threshold. Metastability, however, may cause the comparators to fail to generate the corresponding converter code. In system embodiments, logic is provided to sense the absence of comparator decisions at the end of a predetermined decision period. In response to this absence, the system is configured to substitute the corresponding converter code. In another embodiment, the system is configured to substitute the corresponding converter code when it lies outside a predetermined digital code window.