DC-DC Power Converter Package Layout With Fewer Solder Layers
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Solution Overview
Problem
High-current semiconductor devices face solder layer degradation and mechanical stress due to increased current density and mechanical damage in traditional stacked configurations, leading to device failure.
Innovation Solution
Implementing a side-by-side die configuration or a novel stacked configuration with minimized solder layers, using plated pillars instead of clips, to reduce the number of solder layers and enhance mechanical and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional stacked configuration is used, then vertical integration is achieved, but solder layer degradation and mechanical stress increase due to high current density
Solution Approach 1:
The patent transitions from a vertical stacked configuration to a side-by-side horizontal configuration. The high-side FET and low-side FET are positioned adjacent to each other in the same plane rather than stacked vertically, eliminating multiple solder layers while maintaining electrical connectivity through alternative pathways.
2Device complexity
If multiple solder layers are used for stacked dies, then component integration is achieved, but mechanical damage and device failure risk increase
Solution Approach 1:
The patent extracts and eliminates the intermediate solder layers that connect stacked dies. By removing these vulnerable solder joints, the design reduces mechanical stress points and potential failure modes while maintaining functional integration through direct mounting of FETs to the substrate.
3Force
If clips are used to couple FETs to conductive members, then mechanical attachment is achieved, but solder degradation occurs due to stress concentration
Solution Approach 1:
The patent replaces the mechanical clip system with direct solder-less attachment methods. FETs are mounted directly to the substrate using alternative coupling mechanisms that distribute stress more evenly, eliminating the stress concentration points created by clips that lead to solder joint failure.
Data Source
AI summary
In some examples, a direct current (DC)-DC power converter package comprises a controller, a conductive member, and a first field effect transistor (FET) coupled to the controller and having a first source and a first drain, the first FET coupled to a first portion of the conductive member. The package also comprises a second FET coupled to the controller and having a second source and a second drain, the second FET coupled to a second portion of the conductive member, the first and second portions of the conductive member being non-overlapping in a horizontal plane. The first and second FETs are non-overlapping.