Switching Converter Panic Comparator Transient Response
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Solution Overview
Problem
Buck converters face challenges in achieving a good load transient response, particularly experiencing large undershoots and overshoots due to delays in the panic comparator's reaction to output voltage changes, which cannot be simultaneously minimized.
Innovation Solution
Incorporating a panic comparator with a reset switch, a panic latch, and a timing generator that generates reset and strobe signals to quickly set and reset the panic comparator output, along with a High Pass Filter element to accelerate the response, allowing for early negation of the panic comparator output and reducing delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the panic comparator delay is reduced, then the response speed improves, but the complexity of the circuit increases
Solution Approach 1:
The patent extracts the delay-causing elements from the panic comparator circuit by separating the threshold generation function from the main comparator path. The delay was caused by the time required to generate and stabilize the threshold voltage; by extracting this function into a dedicated circuit block with pre-charged capacitors and separate timing control, the main comparator can respond immediately without waiting for threshold stabilization, thus reducing delay while managing complexity through functional separation.
Solution Approach 2:
The patent applies preliminary action by pre-charging the capacitor that generates the panic comparator threshold voltage before it is needed. This pre-charging action prepares the threshold voltage in advance, eliminating the delay that would otherwise occur while the capacitor charges during normal operation. The reset signal initiates this preliminary charging action, ensuring the threshold is ready immediately when required for comparison.
Data Source
AI summary
A switching converter with improved load transient response is provided, including a panic comparator with a reset switch, a panic latch that is set by an output of the panic comparator and reset in conjunction with a strobe timing, and a timing generator which generates reset and strobe signals. The timing generator may include a gated oscillator, enabled by the panic latch. The panic comparator may include an HPF element, configured to accelerate the panic comparator response. The switching converter may be multi-phase.