Multi-phase Converter Phase Timing Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-phase converters face challenges in controlling frequency and phase timing due to the need for external resistors, which increase complexity, cost, and introduce accuracy issues and noise, and cannot program phases near the peak and valley of the triangle wave, leading to phase timing errors.
Innovation Solution
A multi-phase converter using a two-wire bus with a daisy chain arrangement of phase controllers, where a main control circuit provides clock signals to each phase controller, allowing for sequential delayed clock signals to determine the timing of switched output voltages, eliminating the need for external resistors and improving phase timing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external resistors are used per phase to program phase delay, then phase timing can be controlled, but device complexity and cost increase
Solution Approach 1:
The patent merges the phase timing control function into the controller itself by integrating a delay circuit that generates delayed clock signals internally. This eliminates the need for external resistors per phase, reducing device complexity while maintaining precise phase timing control through the controller's internal delay mechanisms.
Solution Approach 2:
The patent extracts the phase timing control function from external passive components (resistors) and relocates it to the active controller. The controller now contains the delay circuit that previously required external resistors, simplifying the overall system architecture while preserving the ability to program phase delays.
2Ease of operation
If external resistors are used for phase programming, then phase delay can be set, but manufacturing precision is degraded due to component tolerance
Solution Approach 1:
The patent replaces the mechanical/passive resistor-based phase programming with an electronic/digital delay circuit within the controller. This substitution eliminates component tolerance issues associated with external resistors, providing more precise and consistent phase timing control through the controller's internal delay mechanisms.
3Speed
If analog triangle wave is used for clock signaling, then frequency control is achieved, but noise and non-ideal ramp linearity occur
Solution Approach 1:
The patent replaces the analog triangle wave clock signaling with a digital square wave clock signal generated internally by the controller. This substitution eliminates the noise and non-ideal ramp linearity associated with analog triangle waves, providing cleaner and more precise clock signals for frequency control.
4Adaptability or versatility
If phases are programmed near peak and valley of triangle wave, then phase timing flexibility is improved, but phase timing errors increase due to non-ideal wave characteristics
Solution Approach 1:
The patent replaces the triangle wave-based phase programming with a square wave clock signal and internal delay circuit. This allows phases to be programmed at any timing position without the peak and valley constraints of triangle waves, maintaining both flexibility and precision through the controller's internal delay mechanisms.
Data Source
AI summary
A multi-phase converter comprising a plurality of switching circuits each controlled by a phase controller and each providing a switched output voltage to an output node of the converter and wherein each switching circuit under control of the phase controller sequentially provides a switched output voltage to the output node at which an output voltage of the converter is developed; and a main control circuit including a clock circuit for providing a first clock signal to each of the switching circuits and a second lower frequency clock signal to a first of the phase controllers, each phase controller having a delay circuit controlled by the first clock signal to provide a delayed second clock signal for coupling to a next one of the phase controllers and in the case of a last one of the phase controllers, back to the main control circuit, whereby a plurality of sequentially delayed second clock signals is provided, one to each of the remaining phase controllers after the first phase controller to determine when each switching circuit provides the switched output voltage to the output node.