Multimodular Converter Pulse Blocking Staggered Control
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Solution Overview
Problem
Power converters with distributed energy storage experience significant voltage load and rapid voltage changes during pulse locking, leading to increased stress on components and higher costs due to the simultaneous control of all submodules into switching state III, which is not predictable and can result in worst-case scenarios.
Innovation Solution
Implement a staggered control method where only one submodule of an upper and/or lower valve branch is switched to switching state III per time scale, reducing the voltage load to the rate of change of a single submodule, and extending the time required to fully implement a pulse block, thereby minimizing the overall voltage load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all submodules are controlled into switching state III simultaneously during pulse locking, then the converter is reliably blocked in critical states, but the voltage load and rate of change increase significantly causing component stress
Solution Approach 1:
The patent divides the simultaneous switching of all submodules into multiple sequential time echelons. Instead of switching all submodules to state III at once, they are switched in staggered groups across different time intervals, segmenting the voltage load temporal profile and reducing peak stress on components.
Solution Approach 2:
The patent implements periodic action by distributing the submodule switching operations across multiple time echelons with specific time intervals. This periodic staggering of switching events transforms a single high-intensity voltage load into multiple lower-intensity periodic loads, reducing the maximum rate of voltage change.
2Manufacturing precision
If a high number of submodules are used per valve branch to achieve sinusoidal output voltages, then output quality improves, but the voltage load during pulse locking increases proportionally
Solution Approach 1:
The patent segments the switching of multiple submodules across different time echelons. With more submodules per valve branch, the switching is divided into more sequential groups, maintaining high output voltage quality while distributing the voltage load temporal profile to reduce peak rates of change during pulse locking events.
Data Source
Figure 1
Figure 2A~2B
Figure 3A~3B
AI summary
The method involves releasing a pulse barrier due to an error during an operation of a power converter (2). A switching status of a two-pole subsystem of each of a set of valve branches (P1-P3, N1-N3) is controlled in a switching state by the barrier. A switching status of a submodule (SM1) of each valve branch is controlled in another switching state according to expiration of a predetermined time span (delta t), where the time span is equal to a turn-off delay time of a disconnectible semiconductor switch (S1) of the two-pole subsystem.