Power Converter Startup Circuit for Constant-Power In-Rush Limiting
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Solution Overview
Problem
Existing DC-DC power converters face issues with excessive in-rush currents during startup, leading to voltage spikes that can damage components and overheating, particularly in devices with constrained battery space, and require quick startup times without compromising efficiency.
Innovation Solution
Implementing a driver circuit with a variable reference current circuit and power limiting circuit to control the current through the transistor inversely proportional to the voltage across it, maintaining approximately constant power during startup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DC-DC power converter startup is used, then the converter can start operating, but excessive in-rush current spikes occur that can damage components
Solution Approach 1:
The patent applies preliminary action by implementing a soft-start mechanism that gradually enables the power converter circuit rather than immediately applying full power. The controller circuit progressively activates the switch-capacitor network, allowing capacitors to charge in a controlled sequence that prevents sudden current in-rush while still achieving reliable component operation
Solution Approach 2:
The patent uses an intermediary approach by introducing a controller circuit that acts as a mediator between the power source and the power converter circuit. This controller gradually adjusts the activation of switches and monitors voltage levels, interpolating the power transfer process to prevent damaging current spikes while maintaining system reliability
2Loss of time
If power converter startup is accelerated, then startup time is reduced, but overheating occurs that reduces efficiency
Solution Approach 1:
The patent applies dynamics by implementing a dynamic startup sequence that adapts the power transfer rate based on real-time voltage measurements. The controller circuit monitors capacitor charging progress and adjusts switch activation timing accordingly, creating an optimized startup trajectory that minimizes both time and energy loss rather than using a fixed aggressive or conservative approach
Solution Approach 2:
The patent uses periodic action through a multi-phase startup sequence where switches are activated in staged intervals. The controller enables different sets of switches in successive phases, with each phase allowing capacitors to charge to specific voltage thresholds before proceeding to the next phase, creating a rhythmic activation pattern that balances speed and efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach mitigates damaging current spikes, enables quicker startup times, and maintains high efficiency without overheating, ensuring reliable operation in devices with limited battery space.
Implementation Method 1
If the ON resistance, RON, of the FET power switches is 1 milliohm (0.001 ohms), and VIN is 10V, then as a result of Ohm's law (V=I×R), the in-rush current will be a spike of about 10,000 amps
Implementation Method 2
parasitic inductances exist (for example, due to on-die conductor routing and printed circuit board conductor routing) which transform a current spike to a voltage spike in accordance with inductor theory (V=L×dI/dt)
Data Source
AI summary
Circuits and methods for providing a constant, limited power to a transistor of a power converter during a startup period while achieving high efficiency and high performance. In a first embodiment, a driver circuit includes a variable reference current circuit configured to provide a first current inversely proportional to a voltage across the transistor, and a coupled power limiting circuit that enables a second current through the transistor that is proportional to the first current. In a second embodiment, a driver circuit includes a variable reference current circuit configured to provide a first current that increases over a time period of operation as a function of a voltage at a node of the power converter, and a coupled power limiting circuit that enables a second current through the transistor that is proportional to the first current and inversely proportional to a voltage across the transistor.