Cascaded Converter Submodule Testing With Pulse Interference Compensation
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Solution Overview
Problem
Existing testing platforms for cascaded converters are limited in providing diverse testing conditions and control modes, leading to high power supply requirements and low testing efficiency, and fail to effectively suppress voltage pulse interference from nearest level control modulation, increasing complexity and cost.
Innovation Solution
A testing circuit and system for multiple submodules (SMs) with a current generator and testing module group, featuring reverse series connections and current controllers to emulate operating conditions, reduce DC supply voltage requirements, and eliminate pulse voltage interference using feedforward voltage compensation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If additional auxiliary circuits are added to suppress voltage pulse interference, then the interference suppression capability is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent converts the harmful voltage pulse interference into a beneficial feedforward signal. By sampling the pulse voltage and processing it through a low-pass filter, the interference is transformed into a compensation signal that is injected into the current controller to cancel out its harmful effects, thereby eliminating the need for additional auxiliary circuits
Solution Approach 2:
The patent extracts the pulse voltage signal from the system and separates it from the main control loop. By sampling the pulse voltage at the terminal of the tested SM and processing it independently through filtering and compensation, the harmful interference is isolated and handled separately, simplifying the overall circuit structure
2Object-affected harmful factors
If additional auxiliary circuits are added to suppress voltage pulse interference, then the interference suppression capability is improved, but the manufacturing cost increases
Solution Approach 1:
The patent converts the harmful voltage pulse interference into a beneficial feedforward signal. By sampling the pulse voltage and processing it through a low-pass filter, the interference is transformed into a compensation signal that is injected into the current controller to cancel out its harmful effects, thereby eliminating the need for additional auxiliary circuits
Solution Approach 2:
The system uses its own pulse voltage signal to generate the compensation needed to eliminate the interference. The pulse voltage is sampled, filtered, and processed to create a feedforward signal that automatically compensates for the interference without requiring external auxiliary circuits, making the system self-sufficient
3Reliability
If dead time is introduced in switching transients for auxiliary circuit operation, then the switching protection is improved, but the control synchronization deteriorates
Solution Approach 1:
The patent performs preliminary sampling of the pulse voltage signal at the terminal of the tested SM before the switching transient occurs. By sampling the voltage at the optimal moment and processing it through a low-pass filter in advance, the system generates the compensation signal without requiring dead time, ensuring both switching protection and control synchronization
Data Source
AI summary
A testing circuit for multiple SMs of a cascaded converter and a control method thereof are provided. A current generator generates a testing current flowing into a testing module group. The testing module group includes two series-connected testing arms that each contains multiple SMs, or in an alternative way, the testing module group is composed of one or multiple testing units connected in series, and each testing unit includes two testing SMs connected in series reversely. The testing circuit the control method thereof realizes a mission profile emulation of the multiple SMs of the cascaded converter in both inverting and rectifying modes simultaneously to improve a test efficiency. A reverse series connection structure of the two testing SMs offsets a DC component in a capacitor voltage to reduce a power supply voltage required for a test. Dynamic and static control methods under different modulations for the test circuit are provided.