Switching Converter Transistor Activation for Loss Reduction
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Solution Overview
Problem
MOSFETs experience significant losses due to ohmic and capacitive losses, particularly during switching operations, which are influenced by load conditions and switching frequency, necessitating a solution to minimize these losses and turn-off delay times.
Innovation Solution
A circuit arrangement with a transistor arrangement featuring multiple transistors, each with a gate terminal and a control terminal, where the load paths are connected in parallel, and a drive circuit adjusts the activation state of the transistors based on load conditions to optimize ohmic and capacitive losses by varying the number of transistors in different activation states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the switching frequency is increased to improve productivity, then the output per unit time increases, but the switching losses and capacitive losses increase proportionally
Solution Approach 1:
The patent applies dynamics by enabling the drive circuit to adaptively adjust transistor activation states in response to switching frequency and load conditions. This dynamic control allows the system to maintain optimal efficiency across a range of switching frequencies by minimizing capacitive losses through selective transistor deactivation when appropriate.
Solution Approach 2:
The patent implements feedback by using load condition detection to inform the drive circuit's control decisions. The drive circuit receives information about current load conditions and uses this feedback to determine the optimal activation state for each transistor, thereby minimizing losses while maintaining required output levels.
2Loss of energy
If the load current is decreased to reduce ohmic losses, then the power consumption decreases, but the turn-off delay time increases due to reduced charge available for discharging the output capacitance
Solution Approach 1:
The patent applies preliminary action by proactively adjusting the activation state of transistors before switching events based on predicted or detected load conditions. The drive circuit prepares the transistor states in advance to ensure adequate charge/discharge paths are available, reducing turn-off delay even when load current is low.
Solution Approach 2:
The control terminal acts as an intermediary that provides additional control capability beyond the standard gate terminal. This intermediary control path allows the drive circuit to influence the transistor's charge state and switching behavior, helping to manage turn-off delay independent of load current magnitude.
Data Source
AI summary
A switching converter includes a transistor arrangement having a plurality of n transistors, with n≧2, each including a gate terminal, and a load path between a source and a drain terminal, and at least m, with m≦n and m≧1 of the n transistors having a control terminal. The control terminal of each of the m transistors is configured to receive a control signal that adjusts an activation state of the transistor. The load paths of the plurality of n transistors are connected in parallel to form a load path of the transistor arrangement. A drive circuit is configured to adjust the activation state of the m transistors.