Converter Valve FPGA Redundancy Switching Under Crash Conditions
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Solution Overview
Problem
Current solutions for controlling redundancy in valve control systems of converter valves are unreliable, particularly when FPGAs crash, leading to ineffective control over optical emitting modules and instability in system operation.
Innovation Solution
A method and apparatus for controlling redundancy in valve control systems, where each pulse distribution board includes two FPGAs and optical modules, with a monitoring output channel to transmit running state information and ensure efficient control over redundancy, improving switching reliability and fault response speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If FPGA1 controls the data selection module for redundancy switching, then the valve control system can maintain operation during FPGA1 power loss, but when FPGA1 crashes and maintains high-level output, the FPGA2 cannot control the optical module to send trigger pulses
Solution Approach 1:
The patent introduces a monitoring circuit as an intermediary between FPGA1 and the data selection module. This monitoring circuit detects the output state of FPGA1 and controls the enable terminal of the data selection module accordingly. When FPGA1 crashes and maintains high-level output, the monitoring circuit detects this abnormal state and disables FPGA1's control over the data selection module, allowing FPGA2 to take over control without interference from the crashed FPGA1.
2Reliability
If dual FPGA redundancy design is implemented with independent power supplies and oscillators, then system reliability is improved, but the complexity of controlling redundancy switching increases
Solution Approach 1:
The patent implements a feedback mechanism where the monitoring circuit continuously monitors the output state of FPGA1 and provides feedback control to the enable terminal of the data selection module. This automatic feedback control simplifies the redundancy switching logic by eliminating the need for complex software-based switching mechanisms, reducing overall control complexity while maintaining dual FPGA redundancy for improved reliability.
Data Source
AI summary
The present disclosure discloses a method and apparatus for controlling redundancy of a valve control system of a converter valve. The method includes: for each FPGA: in a case that the FPGA receives the on-duty state representing the active state: outputting a high-level control signal to a data selector through the FPGA; in a case that the FPGA receives the on-duty state representing the standby state: outputting a low-level control signal to the data selector through the FPGA, and maintaining a control signal output state of the FPGA and the other FPGA; and in a case that running state information of the other FPGA received by the FPGA through a monitoring output channel is a crash state: outputting a low-level signal to a control port of the other FPGA through the monitoring output channel by the FPGA.