Three Phase Four Wire Interlinking Converter Fault Control

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Solution Overview

Problem

Three-phase four-wire interlinking converters face challenges in accurately detecting and managing short circuits, leading to unnecessary power outages and system deterioration due to voltage unbalance and high short circuit currents, especially when one-line earth faults occur, requiring additional controllers and complex PLL techniques.

Innovation Solution

A method utilizing a new o-axis transform PLL technique and switching combination to electrically isolate fault locations by applying a zero voltage vector to the fault area, determining fault occurrence and area based on output voltage vectors, and using symmetric space vector voltage modulation to control switching states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a circuit breaker is used to eliminate fault sector, then system protection is improved, but unnecessary power outages occur in local area

Engineering Contradiction:
Improvesystem protectionVSAvoidpower outage
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by implementing individual voltage control for each phase through separate PLL techniques. When a short circuit occurs in one phase, only that specific phase is controlled to supply power normally to loads connected to non-short-circuited phases, rather than cutting off all phases. This localized approach ensures that power supply is maintained in unaffected areas while protecting the faulty sector.

Inventive Principle:
Principle #3Local quality

2Measurement precision

If additional controllers are added for individual voltage control, then fault detection accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvefault detection accuracyVSAvoidcontroller quantity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent implements a multi-functional controller that integrates PLL techniques for individual phase voltage control, fault detection, and zero voltage vector allocation within a single control unit. This universal controller handles multiple functions including detecting fundamental wave components of unbalanced voltage, determining fault locations, and controlling switching states, thereby avoiding the need for multiple separate controllers while maintaining accurate fault detection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Device complexity

If traditional PLL techniques are used for unbalanced voltage, then voltage filtering is simplified, but detection accuracy of normal output voltage component deteriorates

Engineering Contradiction:
Improvefiltering complexityVSAvoidvoltage component detection accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent segments the voltage detection process by separately analyzing fundamental wave components of unbalanced voltage for each phase through individual PLL techniques. This segmentation allows the system to accurately detect the magnitude and phase of normal output voltage components while excluding phases creating short-circuits, improving detection accuracy without requiring complex filtering mechanisms.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary processing step that detects fundamental wave components of unbalanced voltage through filtering, then uses PLL techniques to accurately determine the magnitude and phase of normal output voltage components. This intermediary detection mechanism bridges the gap between simple filtering and accurate voltage component measurement, enabling precise fault detection while maintaining system simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Reliability

If zero voltage vector is allocated to fault area, then fault isolation effectiveness is improved, but switching control complexity increases

Engineering Contradiction:
Improvefault isolation effectivenessVSAvoidswitching control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic switching control that automatically adjusts switching states based on real-time fault detection. When a short circuit is detected in a specific phase, the controller dynamically allocates zero voltage vectors to the faulty phase while maintaining normal voltage output for unaffected phases. This dynamic adaptation allows effective fault isolation without requiring complex manual intervention or fixed switching patterns.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage output parameter dynamically by allocating zero voltage vectors to fault areas. Through symmetric space vector voltage modulation, the system adjusts the voltage magnitude and switching states in response to detected faults, transforming the voltage parameter from a constant value to a dynamically controlled variable that adapts to fault conditions, thereby achieving effective isolation with controlled complexity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11641156B2Method for controlling fault using switching technique of three phase four wire interlinking converter
Publication Date: 2023.05.02 RES & BUSINESS FOUND SUNGKYUNKWAN UNIV
  • US11641156B2 patent drawing
  • US11641156B2 patent drawing
  • US11641156B2 patent drawing

AI summary

A method for controlling a fault of a three phase four wire interlinking converter system according to one embodiment of the present disclosure comprises obtaining a first d-q-o coordinate plane based on an internal phase angle of output voltage produced from each phase of an inverter; converting the first d-q-o coordinate plane to a second d-q-o coordinate plane based on the o-axis configured differently from the first d-q-o coordinate plane; obtaining an output voltage vector for determining a fault location by performing d-q transform on the second d-q-o coordinate plane; determining occurrence of a fault and an area related to the fault based on the output voltage vector; and in the occurrence of the fault, allocating a zero voltage vector to the area related to the fault.