Convolution Accelerator Using Resistive Memory Crossbar Arrays
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Solution Overview
Problem
Existing digital circuitry faces challenges in efficiently performing fast convolution computations for large-scale input signals and kernels due to memory limitations, making it difficult to implement efficient convolution operations.
Innovation Solution
The use of hardware-based convolution accelerators that leverage memory crossbar arrays to calculate Fourier Transformations and Inverse Fourier Transformations, allowing for efficient convolution operations by segregating input and kernel matrices into smaller portions and performing matrix multiplication in the frequency domain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If digital circuitry is used to perform convolution computations, then computational flexibility is maintained, but computational speed and energy efficiency deteriorate for large-scale inputs
Solution Approach 1:
The patent replaces digital computational circuits with an analog resistive memory array that directly performs convolution operations through physical electrical relationships. The resistive array exploits the fundamental relationship between row voltage and column current to realize analog multiply-accumulate operations, substituting digital computation with analog physics-based computation that is inherently faster and more energy-efficient for large-scale convolutions
Solution Approach 2:
The patent changes the computational paradigm from digital to analog by utilizing continuous voltage and current parameters in the resistive memory array. This parameter change enables parallel analog computation where multiple multiply-accumulate operations occur simultaneously through electrical signal propagation, dramatically improving computational speed and reducing energy consumption compared to sequential digital operations
2Productivity
If resistive memory array is used for analog computation, then computational speed and energy efficiency improve, but device complexity increases
Solution Approach 1:
The patent makes the resistive memory array universal by programming it with different transformation matrices (such as FFT matrices) to perform various computational tasks. The same physical array can be reconfigured through programming to execute different convolution operations, making it a multi-functional computational engine that handles diverse workloads without requiring separate hardware for each function
Solution Approach 2:
The patent segments large-scale convolution operations into smaller manageable portions by organizing the resistive memory array into a grid of cells that can be selectively activated. The input signal and kernel are divided into segments that map to different rows and columns of the array, enabling parallel processing of multiple segments simultaneously while managing the complexity of large-scale computations
3Productivity
If convolution is performed in frequency domain using FFT, then computational efficiency improves for large-scale inputs, but memory requirements increase
Solution Approach 1:
The patent replaces digital memory storage and retrieval operations with analog signal processing in the resistive memory array. Instead of storing large matrices in digital memory and performing sequential multiplications, the system uses the physical properties of the resistive array to directly compute frequency domain transformations and convolutions, effectively replacing memory-intensive digital operations with memory-efficient analog computation
Solution Approach 2:
The patent merges the functions of memory storage and computation into a single resistive memory array structure. The array simultaneously serves as both the storage medium for transformation matrices and the computational engine for performing matrix-vector multiplications, eliminating the need for separate memory and computation units and reducing overall memory requirements for FFT-based convolutions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the efficiency of convolution computations by utilizing hardware to accelerate Fourier Transformations and Inverse Fourier Transformations, overcoming memory limitations and improving computational speed and energy efficiency.
Implementation Method 1
The fundamental relationship between a row access voltage and a resulting bit line current can act as an analog multiplier of row voltage and memory array cell conductance
Data Source
AI summary
Examples herein relate to convolution accelerators. An example convolution accelerator may include a transformation crossbar array programmed to calculate a Fourier Transformation of a first vector with a transformation matrix and a Fourier Transformation of a second vector with the transformation matrix. A circuit of the example convolution accelerator may multiply the Fourier Transformation of the first vector with the Fourier Transformation of the second vector to calculate a product vector. The example convolution accelerator may have an inverse transformation crossbar array programmed to calculate an Inverse Fourier Transformation of the product vector according to an inverse transformation matrix.