Convolution Block Architecture for Neural Network Processing

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Solution Overview

Problem

Current neural network processing systems face inefficiencies in cell utilization during depth-wise convolution operations, leading to suboptimal performance.

Innovation Solution

A computing system architecture is proposed, featuring a convolution block with a sequence of three convolution layers: a first layer performing 1×1 convolution, a second layer performing n×n convolution on channels, and a third layer performing another 1×1 convolution, which enhances cell utilization and processing efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If depth-wise convolution operation is applied to the multiply-accumulate (MAC) operation device, then the neural network can perform depth-wise convolution, but cell utilization is decreased

Engineering Contradiction:
Improveconvolution operation capabilityVSAvoidcell utilization
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The convolution operation is divided into multiple sequential stages: first convolution layer (1×1 kernel), second convolution layer (n×n kernel), and third convolution layer (1×1 kernel). This segmentation allows each layer to perform specialized operations that collectively achieve depth-wise convolution functionality while maintaining high cell utilization in the MAC operation device

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transforms the single-stage depth-wise convolution operation into a multi-layer architecture that operates across different dimensional spaces. The 1×1 convolutions operate in the channel dimension while the n×n convolution operates in the spatial dimension, creating a dimensional transformation that resolves the utilization conflict

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Device complexity

If a single convolution layer performs depth-wise convolution, then the operation is simple, but processing performance is suboptimal

Engineering Contradiction:
Improveconvolution layer structureVSAvoidneural network processing performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The first convolution layer performs preliminary processing on the input data before it enters the second convolution layer. This preliminary action prepares the data in a format that optimizes subsequent processing, enabling the multi-layer structure to achieve superior performance compared to a single layer

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The three convolution layers are arranged in continuous sequence where the output of each layer immediately becomes the input of the next. This continuous action eliminates idle periods and ensures that the MAC operation device continuously performs useful computations, maximizing processing performance

Inventive Principle:
Principle #20Continuity of useful action

Data Source

PatentUS20250036927A1Computing system for processing neural network and method of operating the same
Publication Date: 2025.01.30 SK HYNIX INC
  • US20250036927A1 patent drawing
  • US20250036927A1 patent drawing
  • US20250036927A1 patent drawing

AI summary

Provided herein may be a computing system and method of operating the same. The computing system may include an operating component including at least one convolution block, and a controller configured to control the operating component to perform convolution operations, wherein the at least one convolution block includes a first convolution layer configured to perform a first convolution operation on input data based on a 1×1 kernel to generate first result data, a second convolution layer configured to perform second convolution operations on 10 respective channels of first result data based on an n×n kernel, where n is a natural number of 2 or greater, and sum result values of the convolution operations to generate second result data, and a third convolution layer configured to perform a third convolution operation on the second result data based on the 1×1 kernel to generate final result data.