Convolution Circuit Utilization with Limited Bus Width
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Solution Overview
Problem
Existing data processing methods for convolution operations in edge AI systems face challenges in maximizing product-sum operation circuit utilization efficiency while minimizing circuit resources, particularly due to limited bus width and the need to support multiple convolution operation accuracy modes.
Innovation Solution
A data processing device and method that perform convolution operations by utilizing a product-sum operation unit, shifter, addition unit, selector, cumulative addition unit, and memory to efficiently process input data of varying bit widths, allowing for flexible switching between different convolution operation accuracy modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of parallel blocks is increased to improve processing speed, then the input bus width of iFmap increases, but the bus width is limited in edge AI systems
Solution Approach 1:
The patent divides the convolution operation into multiple parallel blocks that process different parts of the input data simultaneously. Each block operates with a reduced bus width, and the results are combined through accumulation. This segmentation allows the system to achieve high processing speed without requiring a wide input bus, as each block only needs to access a portion of the data at a time.
Solution Approach 2:
The patent introduces a temporal dimension by processing data in multiple passes. Instead of loading all data at once into a wide bus, the system loads data in smaller chunks across multiple time steps, accumulating results progressively. This transforms a spatial width problem into a temporal sequence problem, allowing high throughput with limited bus width.
2Length of stationary object
If the bus width is limited to fit edge AI system constraints, then the number of parallel pixels is doubled, but the product-sum operation circuit enters empty state and cannot extract sufficient performance
Solution Approach 1:
The patent ensures continuous utilization of product-sum operation circuits by processing multiple blocks in sequence. Even when the bus width is limited and the number of parallel pixels is doubled, the system maintains continuous data flow through the accumulation mechanism. Each block's output feeds into the accumulation register, ensuring that the product-sum circuits remain actively engaged throughout the processing pipeline without entering empty states.
Solution Approach 2:
The patent prepares data in advance by loading it into buffers and organizing it into blocks that can be processed sequentially. This preliminary preparation allows the limited bus width to be efficiently utilized across multiple passes, ensuring that the product-sum operation circuits receive continuous input data and maintain full operational efficiency without idle time.
3Productivity
If the operator utilization efficiency is increased to 100% by doubling the iFmap input bus width and kernel input bus width in 8-bit mode, then the circuit area increases significantly
Solution Approach 1:
The patent designs the data processing device with a universal architecture that can operate in multiple precision modes (4-bit, 8-bit, 16-bit) using the same hardware resources. The product-sum operation circuits are designed to handle different data widths and precision requirements through configurable processing modes, eliminating the need for separate dedicated circuits for each mode. This multi-functionality maintains high operator utilization efficiency across all modes without requiring proportional increases in circuit area.
Solution Approach 2:
The patent implements dynamic configuration of the processing device that allows switching between different operational modes based on the specific application requirements. The system can dynamically adjust the number of parallel blocks, the precision level, and data processing parameters to optimize performance for different tasks. This dynamic adaptability enables the same circuit to achieve high operator utilization efficiency in 8-bit mode without requiring the maximum possible bus width, as the system can scale down resources when operating at lower precision levels.
4Adaptability or versatility
If multiple convolution operation accuracy modes are supported by a shared circuit, then the adaptability improves, but the installation difficulty level increases due to lack of detailed configuration
Solution Approach 1:
The patent implements a configurable architecture where the key parameters such as data width, precision level, and number of parallel blocks can be dynamically adjusted through software control. The system includes configuration registers and control logic that allow the same hardware circuit to be reconfigured for different convolution operation accuracy modes (4-bit, 8-bit, 16-bit) by changing operational parameters rather than requiring physical reconfiguration. This parameter-based configurability maintains high adaptability while simplifying installation and reconfiguration processes.
Data Source
AI summary
There is provided a data processing device 10 that performs a convolution operation of two pieces of input data of 2M×N bits (N is a positive integer and M is a natural number) width with a minimum accuracy of the convolution operation being N bits, and performs processing corresponding to a plurality of the consecutive M, the data processing device 10 including: a product-sum operation unit 101 that performs a product-sum operation according to the value of M; a shifter 102 that performs shift processing on a result of a product-sum operation of the product-sum operation unit 101 in a case where the value of M is not 0; an addition unit 103 that performs addition processing on each output of the shifter 102 or the product-sum operation unit 101 according to the value of M; a selector 105 that selects an output from the addition unit 103 according to the value of M; a cumulative addition unit 106 that cumulatively adds the outputs from the selector 105; and a cumulative addition memory 107 that stores outputs from the cumulative addition unit 106 in a process of a convolution operation.