Convolution Arithmetic Circuit for CNN SoC Efficiency
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Solution Overview
Problem
Convolutional Neural Networks (CNNs) face significant computational challenges when implemented on resource-limited built-in SoC devices due to the large number of convolution arithmetic operations required, making it difficult to perform image recognition tasks efficiently.
Innovation Solution
The proposed solution involves generating an integration coefficient table that reduces the number of convolution arithmetic operations by performing cumulative additions across channels in parallel, using a convolution arithmetic processing circuit and an integration coefficient table generation device to integrate coefficients from multiple channels, allowing for efficient CNN operation on limited resource devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If CNN performs convolution arithmetic operations for each channel separately, then image recognition accuracy is maintained, but the operation amount becomes extremely large
Solution Approach 1:
The patent merges convolution operations across multiple channels by generating an integration coefficient table that combines coefficients from multiple channels. This allows the system to perform a single integrated convolution operation instead of separate operations for each channel, significantly reducing the total operation amount while maintaining recognition accuracy through the integrated coefficient information.
Solution Approach 2:
The patent performs preliminary action by pre-calculating and storing integrated coefficients in an integration coefficient table before the actual convolution operation. This pre-processing step consolidates channel-specific coefficients into integrated coefficients that can be used directly during inference, eliminating the need for repeated separate channel operations.
2Adaptability or versatility
If CNN is implemented on built-in type SoC devices, then device integration is improved, but resource limitations make it difficult to handle large operation amounts
Solution Approach 1:
The patent merges multiple channel operations into a single integrated operation using the integration coefficient table. This reduction in operation count directly addresses the resource constraints of built-in type SoC devices, making CNN implementation feasible on resource-limited hardware while maintaining the adaptability to run on various device types.
3Measurement precision
If multiple convolution operations are performed for each channel, then comprehensive feature extraction is achieved, but processing time increases
Solution Approach 1:
The patent performs preliminary action by pre-computing integrated coefficients that encapsulate feature extraction information from multiple channels. During actual processing, this pre-computed table allows for rapid convolution operations without sacrificing the comprehensive feature extraction capability, thereby significantly reducing processing time.
Solution Approach 2:
The patent merges the feature extraction operations across channels by using integrated coefficients that combine information from multiple channels. This merging allows the system to achieve comprehensive feature extraction in a single operation rather than requiring separate operations for each channel, thus reducing processing time.
Data Source
Figure 1~2A
Figure 2B~2C
Figure 3
AI summary
A semiconductor device includes an image recognition device having a convolution arithmetic processing circuit. The convolution arithmetic processing circuit includes a coefficient register where coefficients of an integration coefficient table are set, a product calculation circuit that calculates products of an input image and the coefficients, a channel register where a channel number of the integration coefficient table is set, a channel selection circuit that selects an output destination of a cumulative addition arithmetic operation on the basis of the channel number, and a plurality of output registers that store a result of the cumulative addition arithmetic operation. The integration coefficient table is a table where a plurality of input coefficient tables are integrated and the integration coefficient table has a size of N x N. The product calculation circuit can calculate data of N x N all at once.