Convolution Circuit Parallel Processing Large Filter Kernels
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Solution Overview
Problem
Existing convolution operation circuits face challenges in performing high-speed processing due to the need for expensive high-end processors when implemented in software and the difficulty in realizing high-performance hardware for complex and hierarchical convolution operations, especially with large filter kernels, which leads to inefficiencies in both serial and parallel processing configurations.
Innovation Solution
A convolution operation circuit is designed with multiple multipliers, shift registers, cumulative adders, and a control unit that enables parallel processing by synchronizing shift operations and data transfer, allowing for efficient handling of large filter kernels and hierarchical connections, thereby achieving high-speed convolution operations with a simple configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If convolution operation is implemented in software on microprocessor, then flexibility and adaptability are improved, but processing speed deteriorates
Solution Approach 1:
The patent replaces software-based convolution operations on microprocessors with dedicated hardware circuitry. The hardware implementation includes parallel multipliers, adders, and memory units that perform convolution operations through electronic circuit operations rather than software execution, thereby achieving high-speed processing while maintaining configurability through programmable control logic.
2Speed
If high-performance hardware is designed for complex hierarchical convolution operations, then processing speed is improved, but device complexity increases
Solution Approach 1:
The patent divides the complex hierarchical convolution operation into multiple stages and functional blocks. Each stage processes a specific layer or feature map, with dedicated multipliers, adders, and memory units for each stage. This segmentation allows parallel processing of different layers simultaneously, achieving high speed while keeping individual circuit blocks manageable in complexity.
Solution Approach 2:
The patent exploits the hierarchical structure of convolutional neural networks by organizing computation in multiple dimensions - spatial dimensions for feature map processing and depth dimension for layer-wise operations. This dimensional organization enables parallel processing across different layers and feature maps, improving throughput without proportionally increasing circuit complexity.
3Measurement precision
If large filter kernels are used in convolution operation, then recognition accuracy is improved, but processing time increases
Solution Approach 1:
The patent segments the large filter kernel convolution operation into multiple smaller computational blocks that can be processed in parallel. The filter kernel is divided into sub-kernels, and the convolution operation is performed in multiple passes with intermediate results stored in memory, allowing parallel processing of different regions of the feature map simultaneously.
Solution Approach 2:
The patent performs preliminary processing of the filter kernel and input feature map to prepare data in advance. Filter kernel coefficients are pre-loaded into dedicated register files, and input feature maps are pre-processed and stored in buffer memory, enabling the convolution operation to proceed without repeated memory access delays and reducing overall processing time.
Data Source
AI summary
In a convolution operation circuit, a first and a second shift registers provide data to a first and a second inputs of a plurality of multipliers, a first and a second storage units store data to be supplied to the first and the second shift registers, a plurality of cumulative adders accumulate output from the plurality of multipliers, a third storage unit latches output from the plurality of cumulative adders at predetermined timing, a fourth storage unit stores data to be stored in the first and the second storage units and data output from the third storage unit, and a control unit sets data stored in the first and the second storage units to the first and the second shift registers at predetermined timing, causes the first and the second shift registers to perform shift operations in synchronization with an operation of the cumulative adder.