Convolution Circuit Shared Memory Sum Register

The patent divides the convolution computation process into multiple stages using separate buffer regions. The input buffer stores input data, the weight buffer stores convolution weights, and the output buffer stores results. This segmentation allows efficient data flow management and reduces redundant memory access, thereby lowering power consumption while maintaining computation capability.

The patent introduces a time dimension by implementing a pipeline architecture where multiple convolution operations can be executed concurrently at different stages. The sum register accumulates partial results over time, enabling parallel processing of multiple input pixels through the same convolution kernel, thus maintaining high computation capability while reducing per-operation power consumption.

The patent pre-loads input data into the input buffer and convolution weights into the weight buffer before computation begins. This preliminary data preparation ensures that during the actual convolution operation, the computation unit can access all required data immediately without waiting for memory access, thereby reducing processing time while maintaining full computation capability.

The sum register continuously accumulates partial convolution results as each input pixel is processed. The pipeline architecture ensures that the computation unit operates continuously without idle cycles, processing multiple input pixels through the same convolution kernel in sequence. This continuous operation maximizes computation capability while minimizing processing time.

The patent implements a universal buffer structure where the same memory regions (input buffer, weight buffer, output buffer) are reused across multiple convolution operations. The sum register serves as a universal accumulator that can hold partial results for any convolution operation. This multi-functionality allows the system to maintain high computation capability while using a fixed, limited amount of space.

The patent implements a sliding window approach where the sum register accumulates partial results and then discards completed results to make space for new computations. The buffer regions are continuously reused and recovered for new convolution operations after their data is processed. This dynamic allocation and recovery of space allows efficient processing of large data volumes with limited physical memory.