Convolution and Diagonal Accumulation SRAM for Neural Network Processing
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Solution Overview
Problem
Deep neural network models require significant computational resources and memory, making them unsuitable for devices with limited resources like smartphones and IoT devices without compression, which leads to increased power consumption and complexity.
Innovation Solution
A neural network device incorporating a convolution SRAM that performs accumulation peripheral operations and a diagonal accumulation SRAM, along with a multiplexer array and addition array operator, to enhance processing speed and reduce memory usage through sparsity processing and efficient data handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If deep neural network models are used with large numbers of layers and parameters, then model performance is improved, but computational resources and memory requirements increase significantly
Solution Approach 1:
The patent divides the neural network computation into separate functional blocks: convolution SRAM for weight storage and multiplication, accumulation peripheral operators for summation, and diagonal accumulation SRAM for sparse matrix operations. This segmentation allows each component to be optimized independently and reduces overall system complexity while maintaining model performance.
Solution Approach 2:
The patent extracts and utilizes sparsity characteristics of neural network weight matrices by implementing diagonal accumulation SRAM that processes only non-zero elements. This extraction of essential information reduces computational complexity and memory requirements while preserving the core functionality needed for accurate inference.
2Quantity of substance
If deep neural network models are deployed on devices with limited computational resources, then memory usage is reduced through compression, but processing speed decreases
Solution Approach 1:
The patent merges multiple operations into unified hardware structures: the convolution SRAM combines weight storage and multiplication functions, while the accumulation peripheral operators integrate addition and accumulation operations. This merging reduces the number of separate computational steps and improves processing speed despite reduced model size.
Solution Approach 2:
The patent implements preliminary compression and sparsification of neural network models before deployment, extracting only the essential weight information needed for inference. This preliminary action reduces memory footprint and enables faster processing on resource-constrained devices without significantly compromising accuracy.
3Quantity of substance
If neural network models are compressed to fit limited device memory, then memory requirements are reduced, but computational complexity increases
Solution Approach 1:
The patent applies different computational strategies to different parts of the neural network based on their specific requirements. Dense convolutional layers use standard SRAM-based multiplication, while sparse matrix operations use diagonal accumulation SRAM. This localized optimization reduces overall computational complexity while maintaining necessary processing capabilities.
Data Source
AI summary
A neural network device including a convolution static random access memory (SRAM) configured to output a first operation value and a second operation value 1. An accumulation peripheral operator configured to perform an accumulation peripheral operation on the first and the second operation values, a multiplexer array configured to select and output an output value according to a selection signal, a diagonal accumulation SRAM configured to perform a bitwise accumulation of variable weight values and a spatial-wise accumulation operation on an input, a diagonal movement logic, and an addition array operator configured to perform an addition operation of output values of the diagonal movement logic subsequent to a shift operation, the multiplexer array selects any one of an output value of the accumulation peripheral operator and an output value of the addition array operator according to the selection signal and outputs the selected output value to the diagonal accumulation SRAM.