Neural Network Convolution Folding for Small-Channel Alignment

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Solution Overview

Problem

The computing performance of convolution operations in neural network models is hindered by resource wastage due to alignment limitations in parallel operation units and redundant computing from instruction alignment, particularly when the output and input channel dimensions of filters are small.

Innovation Solution

The solution involves dimension folding of convolution filters, rearranging data dimensions to optimize the convolution operation by synthesizing multiple extended filters into a single folding filter, which aligns with hardware requirements and reduces redundant computing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional convolution operation is used with small output channel dimension, then hardware alignment requirements are met, but resource wastage occurs due to limitation of quantity alignment of parallel operation units

Engineering Contradiction:
Improvecomputing performanceVSAvoidresource wastage
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent applies dimension folding to transform the convolution operation by rearranging data dimensions. Specifically, it folds the width and/or height dimensions to the input channel dimension, changing the dimensional structure of the convolution kernel. This allows small output channel dimensions to be mapped to larger effective dimensions that align with hardware parallel operation unit quantities, thereby eliminating resource wastage while maintaining computing performance.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If conventional convolution operation is used with small input channel dimension, then hardware alignment is satisfied, but redundant computing occurs due to limitation of vectorization alignment of instruction sets

Engineering Contradiction:
Improvecomputing performanceVSAvoidredundant computing
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent folds the width and/or height dimensions of the convolution kernel to the input channel dimension. This dimensional transformation rearranges data so that the input channel dimension becomes larger and aligns with instruction set vectorization requirements. By doing so, it satisfies hardware alignment constraints and eliminates redundant computing while preserving the original convolution computation accuracy.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If filter dimensions are folded to align with hardware requirements, then parallel operation unit utilization is improved, but data rearrangement complexity increases

Engineering Contradiction:
Improveparallel operation unit utilizationVSAvoiddata rearrangement complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent performs dimension folding and data rearrangement as a preliminary action before the actual convolution operation. The convolution kernel is pre-transformed by folding width and/or height dimensions to the input channel dimension, creating a folded kernel that is ready for efficient hardware execution. This pre-processing approach simplifies the main convolution operation by ensuring all data is already aligned with hardware requirements, thereby improving parallel operation unit utilization without significantly increasing overall system complexity.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20250348720A1Data processing apparatus and method for executing neural network model, and related products
Publication Date: 2025.11.13 CAMBRICON TECH CO LTD
  • US20250348720A1 patent drawing
  • US20250348720A1 patent drawing
  • US20250348720A1 patent drawing

AI summary

A data processing apparatus may be included in a combined processing apparatus as a computing apparatus. The combined processing apparatus may further include an interface apparatus and other processing apparatus. The computing apparatus interacts with other processing apparatus to jointly complete a computing operation specified by a user. The combined processing apparatus may further include a storage apparatus. The storage apparatus is connected to the computing apparatus and other processing apparatus, respectively. The storage apparatus is configured to store data of the computing apparatus and other processing apparatus. The solution optimizes a convolution operation of a multi-dimensional array and improves operation processing efficiency.