Convolution Accelerator Iteration Engine for Large Kernel Computation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional convolutional accelerators face inefficiencies when handling kernel sizes larger than their defined dimensions, leading to increased overhead, complexity, and power consumption due to frequent memory access and software-implemented kernel decomposition.
Innovation Solution
The implementation of an iteration engine within the convolutional accelerator that iteratively computes convolutions using kernel decomposition, allowing for kernels of varying sizes without reprogramming the hardware architecture, by reusing and streaming data in an iterative manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software-implemented kernel decomposition is used to handle kernels larger than defined dimensions, then adaptability to varying kernel sizes is improved, but device complexity and power consumption increase due to frequent memory access and software overhead
Solution Approach 1:
The large kernel is decomposed into multiple smaller sub-kernels that can be processed by the fixed-dimension convolutional accelerator. The iteration engine divides the kernel decomposition into manageable segments, allowing the hardware to process each sub-kernel independently while maintaining support for varying overall kernel sizes.
Solution Approach 2:
The iteration engine employs periodic iteration to systematically process each sub-kernel in sequence. By cycling through sub-kernels and reusing the same hardware architecture repeatedly with different kernel segments, the system achieves adaptability without requiring architectural reconfiguration for each kernel size.
2Productivity
If frequent memory access is performed to handle large kernels, then computation capability is improved, but power consumption increases
Solution Approach 1:
Kernel data and feature map data are pre-loaded into on-chip buffers before the convolution computation begins. This preliminary action allows the computation engine to process multiple sub-kernels using cached data, significantly reducing the frequency of external memory accesses and associated power consumption.
Solution Approach 2:
The iteration engine maintains continuous computation by systematically processing each sub-kernel in sequence without idle gaps. Data is streamed continuously through the computation pipeline, and the iteration engine ensures that the convolution engine remains actively engaged in useful computation throughout the processing of all sub-kernels.
3Adaptability or versatility
If architectural reconfiguration is performed to support different kernel sizes, then adaptability is improved, but device complexity and reprogramming overhead increase
Solution Approach 1:
The convolutional accelerator is designed with a universal fixed-dimension architecture that can process any kernel size through the iteration engine's decomposition mechanism. The same hardware structure serves multiple functions by processing different sub-kernel configurations, eliminating the need for architectural reconfiguration while maintaining adaptability to varying kernel sizes.
Data Source
Figure 1~2
Figure 3
Figure 4
AI summary
A convolutional accelerator (112) includes a feature line buffer, a kernel buffer, a multiply-accumulate cluster, and iteration control circuitry (114). The convolutional accelerator (112), in operation, convolves a kernel with a streaming feature data tensor. The convolving includes decomposing the kernel into a plurality of sub-kernels and iteratively convolving the sub-kernels with respective sub-tensors of the streamed feature data tensor. The iteration control circuitry (114), in operation, defines respective windows of the streamed feature data tensors, the windows corresponding to the sub-tensors.