Convolution Memory Layout Using MSB Coefficients to Cut Power

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Existing information processing devices face challenges in reducing power consumption during neural network operations, particularly in convolution operations.

Innovation Solution

The implementation of a storage section that stores data in word units and performs convolution operations using most significant bit data, combined with post-processing operations, to optimize data access and reduce power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional memory access methods are used in neural network convolution operations, then data processing can be performed, but power consumption increases due to frequent memory access

Engineering Contradiction:
Improvepower consumptionVSAvoiddata processing efficiency
Core Design Contradiction:
Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-fetching and storing multiple sets of coefficient data (first coefficient data, second coefficient data, third coefficient data) into the memory before they are actually needed for convolution operations. This allows the convolution operation unit to perform multiple convolution operations using the pre-stored data without needing to access external memory repeatedly, thereby reducing power consumption while maintaining processing efficiency

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the coefficient data into multiple distinct sets (first coefficient data, second coefficient data, third coefficient data) that are stored separately in the memory. Each set can be independently accessed and used for different convolution operations, allowing the system to optimize memory access patterns and reduce the frequency of power-consuming memory accesses

Inventive Principle:
Principle #1Segmentation

2Speed

If more coefficient data is stored in memory for efficient convolution operations, then processing speed improves, but memory usage increases

Engineering Contradiction:
Improveconvolution operation speedVSAvoidmemory storage capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The patent implements a dynamic memory management strategy where the memory stores multiple sets of coefficient data that can be selectively used based on the specific convolution operation being performed. The system dynamically switches between different sets of pre-stored coefficient data (first, second, and third coefficient data) depending on the operation requirements, optimizing both speed and memory utilization without requiring permanent storage of all possible data sets

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20260057215A1Information processing device
Publication Date: 2026.02.26 SONY SEMICON SOLUTIONS CORP
  • US20260057215A1 patent drawing
  • US20260057215A1 patent drawing
  • US20260057215A1 patent drawing

AI summary

An information processing device according to an embodiment of the present disclosure includes: a storage section that is configured to store a plurality of pieces of word data each including at least one of a piece of processing target data or a piece of weighting coefficient data, and is configured to be accessed in word data units; a convolution operation section that is configured to perform a convolution operation on the basis of the piece of processing target data and the piece of weighting coefficient data; and a post-processing operation section that is configured to perform a predetermined operation on the basis of an operation result of the convolution operation and store the operation result as the piece of processing target data in the storage section. The piece of weighting coefficient data includes a plurality of pieces of coefficient data each including a plurality of pieces of bit data. The plurality of pieces of word data includes a piece of first word data including two or more pieces of most significant bit data provided side by side, the two or more pieces of most significant bit data being in two or more pieces of coefficient data among the plurality of pieces of coefficient data.