Convolution Circuit Memory Allocation for Neural Network Efficiency
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Solution Overview
Problem
Existing data processing systems for neural networks face challenges with high power consumption, longer processing times, and increased space usage due to large amounts of data during convolution computations.
Innovation Solution
A data processing method and circuit that efficiently allocates input data across multiple memories, dividing it into partial data segments based on available storage space, allowing for effective memory utilization and improved computation efficiency through strategic storage and processing configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If input data is stored in a single memory structure, then the memory access is simple, but the memory space usage is inefficient and computation efficiency is reduced
Solution Approach 1:
The patent divides input data into multiple segments (first partial data, second partial data, etc.) and stores them in different memory addresses or memory structures. Each segment corresponds to specific coordinate positions in the input data, allowing parallel access and computation without requiring a single large memory block, thus improving computation efficiency while managing memory effectively.
Solution Approach 2:
The patent introduces a multi-dimensional memory allocation strategy where data is organized not only by linear memory addresses but also by coordinate information (row and column indices). This dimensional organization allows the system to access and process data from multiple perspectives simultaneously, improving both memory utilization and computation efficiency.
2Speed
If all input data is loaded into memory at once, then processing is faster, but power consumption and space usage increase
Solution Approach 1:
The patent loads and processes data in partial segments rather than loading all data at once. By processing first partial data, second partial data, and other segments sequentially or in parallel batches, the system maintains high processing speed while using only the necessary memory space at each step, thereby reducing power consumption and space usage compared to loading the entire dataset simultaneously.
Solution Approach 2:
The patent performs preliminary organization of input data into segmented structures with associated coordinate information before processing. This pre-organization allows the computation unit to access only the required data segments for each computation step without needing to load or search through the entire dataset, improving processing speed while minimizing memory usage and power consumption.
3Productivity
If data is stored with detailed coordinate information, then data retrieval is more efficient, but memory space usage increases
Solution Approach 1:
The patent designs a memory structure where the same storage unit serves multiple functions: storing data values, their coordinate information (row and column indices), and enabling both sequential and random access patterns. This multi-functional design allows efficient data retrieval with minimal additional space overhead, as the coordinate information is integrated into the storage structure rather than requiring separate metadata areas.
Solution Approach 2:
The patent implements a nested data structure where coordinate information is embedded within or alongside the data values in a hierarchical manner. This nesting allows the system to retrieve data efficiently using coordinate information without requiring separate dedicated storage for metadata, thus improving retrieval efficiency while minimizing additional memory space consumption.
Data Source
AI summary
A data processing method and circuit based on convolution computation are provided. In the data processing method, a shared memory structure is provided, convolution computation of data in batches or duplicated data is provided, an allocation mechanism for storing data into multiple memories is provided, and a signed padding mechanism is provided. Therefore, a flexible and efficient convolution computation mechanism and structure are provided.