Convolution Multiplier Circuit Layout for Lower Power and Wiring Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current hardware solutions for convolution computing in AI technologies face high power consumption and large wiring area due to repeated read and write operations and complex multiplier structures in convolvers.
Innovation Solution
A convolution circuit with a specific design that includes multipliers, a first adder, a second adder, and an adder tree circuit, which reduces the number of full-adders by performing operations on data output by encoder groups and using a computing constant, thereby reducing power consumption and wiring area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated convolver with multiple multipliers and adders is designed to directly implement convolution computing, then convolution computing capability is improved, but power consumption and wiring area are increased due to complex multiplier structures
Solution Approach 1:
The weight parameter is segmented into odd bits and even bits, with different processing paths. The odd bit multiplication results are processed through the adder tree circuit, while even bit multiplication results are handled separately, reducing the computational burden on the adder tree circuit and thereby reducing power consumption.
Solution Approach 2:
The even bit multiplication results are pre-computed and stored before being added to the odd bit multiplication results. This preliminary action allows the adder tree circuit to focus only on processing odd bit results, reducing its complexity and power consumption while maintaining overall computing capability.
2Productivity
If a dedicated convolver with multiple multipliers and adders is designed to directly implement convolution computing, then convolution computing capability is improved, but wiring area is increased due to complex multiplier structures
Solution Approach 1:
The weight parameter is segmented into odd bits and even bits, with different processing paths. The odd bit multiplication results are processed through the adder tree circuit, while even bit multiplication results are handled separately, reducing the computational burden on the adder tree circuit and thereby reducing wiring area.
Solution Approach 2:
The even bit multiplication results are pre-computed and stored before being added to the odd bit multiplication results. This preliminary action allows the adder tree circuit to focus only on processing odd bit results, reducing its complexity and wiring area while maintaining overall computing capability.
3Productivity
If repeated read and write operations are performed on data in general neural-network processing unit, then matrix multiplication calculation is implemented, but power consumption is increased
Solution Approach 1:
The even bit multiplication results are pre-computed and stored in advance, eliminating the need for repeated read operations during the convolution computing process. This reduces memory access frequency and associated power consumption while maintaining calculation capability.
Data Source
Figure 1~3
Figure 4~5
Figure 6
AI summary
Embodiments of this application provide a convolution circuit, a convolution computing method, a chip, and an electronic device, applied to the field of chip technologies, to resolve problems of high power consumption and a large wiring area of a convolution circuit in an existing convolver. The convolution circuit includes a plurality of multipliers, a first adder coupled to the plurality of multipliers, and a second adder coupled to the first adder. Each multiplier includes a plurality of precoders, a plurality of encoder groups, and an adder tree circuit. Each precoder is in a one-to-one correspondence with one encoder group. Output ends of the plurality of encoder groups and input lines of the adder tree circuit are of a same quantity and in a one-to-one correspondence. In addition, the adder tree circuit is coupled to the first adder. The second adder is further coupled to a memory. A partial product that is related only to a weight parameter may be first accumulated with a constant 1 in the multiplier, and then added to results output by adder tree circuits in the second adder, to reduce an area and power consumption of the adder tree circuit.