Convolution Neural Network Hardware with Kernel Resistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Neuromorphic devices based on Von-Neumann architecture face delays and high power consumption due to the need for central processing unit access to memory during data pattern calculations in neural network systems.
Innovation Solution
A convolution neural network with a hardware configuration that includes kernel resistors with fixed resistance values and a filtering processor, along with a pooling processor, to facilitate efficient data processing and compression, reducing the reliance on software processing and enhancing processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If neural network system uses Von-Neumann architecture to calculate data patterns, then processing can be performed through central processing unit, but processing time is delayed and power consumption is high
Solution Approach 1:
The patent replaces the software-based Von-Neumann processing system with a hardware-based neuromorphic system that uses physical circuits to perform neural network operations. The computing device includes input neurons, output neurons, and synapses implemented as physical circuits that directly compute pattern data through electrical signals, eliminating the need for software execution and memory access cycles.
Solution Approach 2:
The computing device is segmented into distinct functional components: input neurons for receiving input data, output neurons for producing results, and synapses for computing weighted sums. Each component is implemented as a separate circuit module that can operate independently and in parallel, improving processing throughput and reducing bottlenecks.
2Productivity
If neural network system uses Von-Neumann architecture, then central processing unit can access memory device, but heavy power consumption occurs
Solution Approach 1:
The patent replaces the high-power Von-Neumann architecture with a low-power neuromorphic hardware system. The synapses are implemented as analog circuits that compute weighted sums through parallel resistor networks, eliminating the need for sequential memory access and complex arithmetic operations that consume significant power in traditional systems.
Solution Approach 2:
The system changes the operational parameters from digital binary operations to analog continuous voltage levels. The synapses use variable resistance values to represent weights, and computations are performed through analog signal processing rather than digital arithmetic, significantly reducing power consumption while maintaining computational capability.
3Productivity
If hardware configuration with kernel resistors is used, then convolution operations can be performed directly, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into unified hardware components. The synapses perform both weight storage (through resistance values) and weighted sum computation (through parallel circuit connections) simultaneously. The input neurons and output neurons are integrated with the synapse circuits, eliminating the need for separate memory and processing units.
Solution Approach 2:
The hardware configuration uses universal building blocks that can perform multiple functions. The synapse circuits can be configured with different resistance values to implement different kernel weights, and the same circuit structure handles both convolution and pooling operations by adjusting connection patterns and resistance values.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables faster data processing and reduced power consumption by performing convolution and pooling operations directly in hardware, improving the efficiency of pattern recognition and learning in neuromorphic devices.
Implementation Method 1
a plurality of kernel resistors having fixed resistance values, each of the kernel resistors corresponding to one of the plurality of input pixels
Implementation Method 2
a filtering processor electrically connecting the plurality of sensors to the plurality of input pixels
Data Source
AI summary
A neuromorphic device including a convolution neural network is described. The convolution neural network may include an input layer having a plurality of input pixels, a plurality of kernel resistors, each of the kernel resistors corresponding to one of the plurality of input pixels, and an intermediate layer having a plurality of intermediate pixels electrically connected to the plurality of kernel resistors.