Neural Network Convolution Redundancy Reduction via Base Planes

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Solution Overview

Problem

Current neural network convolution operations are inefficient due to redundant calculations caused by low-bit precision weights, leading to increased computing resources and time consumption, especially in resource-limited environments.

Innovation Solution

The method involves generating base planes from available weight values of a weight kernel, determining target regions based on weight element offsets, and performing accumulation operations using shift and addition instead of multiplication, to reduce redundancy and optimize convolution operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If low-bit precision weights are used in convolution operations, then device complexity and computing resource consumption are reduced, but calculation accuracy and network performance deteriorate due to redundant operations

Engineering Contradiction:
Improvecomputing resource consumptionVSAvoidcalculation accuracy
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent applies preliminary action by pre-calculating base planes from the weight kernel before the actual convolution operation. The base planes are generated in advance using available weight values, and then reused during the convolution process through accumulation operations. This eliminates redundant calculations while maintaining accuracy, as the base planes are computed once and then efficiently accumulated with input feature maps.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If traditional multiplication operations are performed for each weight element, then calculation accuracy is maintained, but processing speed and efficiency deteriorate due to redundant multiplications

Engineering Contradiction:
Improvecalculation accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent merges multiple multiplication operations into a single accumulation operation. Instead of performing separate multiplication operations for each weight element, the method combines them by accumulating values from base planes that have been pre-computed. This merging of operations significantly reduces the number of computational steps while maintaining the same mathematical result, thereby improving processing speed without sacrificing accuracy.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent changes the computational parameter from multiplication to accumulation (addition). By transforming the operation type from multiplication to accumulation, the patent exploits the property that accumulation is computationally less expensive and can be more efficiently implemented in hardware. This parameter change maintains numerical accuracy while dramatically improving processing speed.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If redundancy reduction techniques are applied, then processing efficiency is improved, but device complexity increases due to additional base plane generation and management

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidoperation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the weight kernel into base planes based on available weight values. By dividing the weight kernel into discrete base planes that can be independently generated and managed, the patent enables efficient reuse of these segments during convolution. This segmentation reduces overall complexity by organizing the computation into reusable units rather than requiring full recalculation for each operation.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20220051084A1Method and apparatus with convolution operation processing based on redundancy reduction
Publication Date: 2022.02.17 SAMSUNG ELECTRONICS CO LTD
  • US20220051084A1 patent drawing
  • US20220051084A1 patent drawing
  • US20220051084A1 patent drawing

AI summary

A processor-implemented neural network layer convolution operation method includes: obtaining a first input plane of an input feature map and a first weight plane of a weight kernel; generating base planes, corresponding to an intermediate operation result of the first input plane, based on at least a portion of available weight values of the weight kernel; generating first accumulation data based on at least one plane corresponding to weight element values of the first weight plane among the first input plane and the base planes; and generating a first output plane of an output feature map based on the first accumulation data.