Convolutional Computing Accelerator Shared Cache Matrix Expandability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing convolutional computing accelerators require higher cache capacity and input bandwidth due to independent caching and transmission of input data to each computing unit, limiting the expandability of the computing matrix.
Innovation Solution
A convolutional computing accelerator design where input data is loaded into a shared cache and distributed to multiple adjacent computing units in a row, allowing them to perform convolutional computations in a single clock cycle using pre-stored convolutional kernels, thereby reducing the need for multiple input channels and improving expandability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If input data is independently cached for each computing unit, then each computing unit can directly receive input data, but the cache capacity and input bandwidth requirements increase significantly
Solution Approach 1:
The patent merges the independent cache resources of multiple computing units into a shared cache system. Specifically, multiple computing units in the same row share a common first cache, and computing units in different rows share a second cache. This consolidation reduces the total cache capacity required while maintaining efficient data access through shared memory resources.
Solution Approach 2:
The shared cache is designed to serve multiple computing units simultaneously, making it a universal resource. The first cache serves multiple computing units within a row, and the second cache serves multiple rows of computing units. This multi-functional cache structure eliminates the need for separate dedicated caches for each computing unit, reducing overall cache capacity requirements.
2Ease of operation
If input data is independently transmitted to each computing unit, then data transmission is straightforward, but the input bandwidth requirements increase
Solution Approach 1:
The patent merges multiple independent data transmission channels into a shared transmission path. Instead of providing separate input channels to each computing unit, the system uses a unified input interface that transmits data to the shared first cache, which then distributes data to multiple computing units. This consolidation significantly reduces the input bandwidth requirements.
Solution Approach 2:
The shared first cache acts as an intermediary between the input interface and multiple computing units. Data is transmitted once to the first cache, which then serves as a distribution point, eliminating the need for multiple parallel transmission channels. This intermediary structure reduces input bandwidth requirements while maintaining efficient data delivery to all computing units.
3Speed
If each computing unit has dedicated cache and input channel, then data access is fast and direct, but the computing matrix expandability is limited
Solution Approach 1:
The shared cache structure provides a universal data storage resource that can serve any number of computing units added to the matrix. When the computing matrix is expanded by adding more computing units, the existing shared cache continues to serve all units without requiring proportional increases in dedicated cache resources per unit. This universal structure enables easy matrix expansion.
Solution Approach 2:
The patent implements a dynamic cache sharing architecture where the cache resources are flexibly allocated among computing units based on actual needs. The shared first cache and second cache can dynamically serve different numbers of computing units in different rows, allowing the system to adapt to varying matrix configurations and expansion scenarios without structural redesign.
Data Source
AI summary
Embodiments of this application relate to a convolutional computing accelerator, a convolutional computing method, and a convolutional computing device, which belong to the technical field of electronic circuits. The convolutional computing accelerator includes: a controller, a computing matrix, and a first cache. The computing matrix comprising at least one row of computing units, each row of computing units comprising at least two adjacent connected computing units. The controller is configured to control input data of each row of computing units to be loaded into the first cache, and to control the input data loaded into the first cache to be inputted into the two adjacent computing units in a corresponding row. Each of the computing units in the corresponding row is configured to perform, in a first clock cycle, a convolutional computation based on received input data and a pre-stored convolutional kernel.