Convolutional Code Rate Matching With a Universal Interleaver
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing rate matching circuits for convolutional codes in mobile communication systems have high complexity and require different interleavers for different parity bit streams, leading to performance degradation and increased complexity in channel encoders.
Innovation Solution
Implementing a rate 1/3 tail-biting convolutional code with a constraint length k=7 and generator polynomial [133, 171, 165] using identical interleavers for all coded bit streams, and a rate-matching circuit that outputs parity bits in group-multiplexed format, allowing for puncturing or repeating to match the data transmission channel rate, thereby reducing complexity and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different interleavers are used for different parity bit streams in conventional rate matching circuits, then the performance degradation during channel decoding is prevented, but the device complexity increases
Solution Approach 1:
The patent merges the functionality of multiple different interleavers into a single universal interleaver that processes all parity bit streams uniformly. This is achieved by applying the same interleaving pattern to all three parity bit streams from the rate 1/3 convolutional encoder, thereby reducing device complexity while maintaining the ability to prevent performance degradation through proper rate matching.
Solution Approach 2:
The patent creates a universal interleaver that serves multiple functions: it interleaves all parity bit streams from different encoder outputs using the same structure. This universal approach simplifies the overall system architecture while still achieving the desired performance by combining the interleaved streams with the information bits in a controlled manner for rate matching.
2Reliability
If multiple different interleavers are implemented for various coded bit streams, then performance degradation is prevented, but the channel encoder complexity increases
Solution Approach 1:
The patent combines multiple interleaving operations into a single interleaving stage that processes all coded bit streams uniformly. By using one interleaver structure for all parity bit streams rather than multiple different interleavers, the channel encoder complexity is reduced while maintaining performance through the unified interleaving and subsequent rate matching process.
3Adaptability or versatility
If conventional rate matching circuits with bit-multiplexing are used, then data transmission rate matching is achieved, but the device complexity increases
Solution Approach 1:
The patent extracts the rate matching function from a complex bit-multiplexing circuit and implements it through a simpler selection process. Instead of using multiple interleavers followed by complex bit-multiplexing, the invention uses a single interleaver followed by a straightforward selection of information bits and interleaved parity bits based on the target code rate, thereby achieving adaptability with reduced complexity.
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.