Convolutional Interleaver Using Burst Memory and Local Buffering
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Solution Overview
Problem
Conventional convolutional interleavers are inefficient in using memory resources, particularly in burst modes, and are costly due to the reliance on external SRAM chips, which can compromise other applications and do not effectively utilize available memory technologies.
Innovation Solution
A system comprising two integrated circuits, one with local memory and an address generator, and another with burst-capable memory, where data is written and read in bursts, optimizing memory access patterns to improve efficiency and reduce resource usage, utilizing multi-port memory and cache memory to emulate register shifts efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If external SRAM chips are used to implement convolutional interleavers, then memory capacity is sufficient for large interleavers, but cost increases and other applications are compromised
Solution Approach 1:
The patent divides the interleaver implementation into two segments: on-chip logic resources for control and addressing, and off-chip burst-capable memory for data storage. This segmentation allows each component to be optimized independently, using affordable external memory while maintaining efficient on-chip resource utilization.
Solution Approach 2:
The patent introduces an intermediary interface layer between the FPGA and external memory that implements burst-capable access patterns. This intermediary translation layer enables the system to utilize inexpensive external memory effectively by bridging the gap between sequential logic requirements and parallel memory capabilities.
2Reliability
If conventional convolutional interleavers are implemented, then data transmission is protected from noise, but memory access efficiency is low
Solution Approach 1:
The patent changes the memory access parameters from sequential single-word transactions to parallel burst transactions. By modifying the access pattern to match the inherent structure of convolutional interleaving, the system achieves both reliable data protection and high memory access efficiency simultaneously.
Solution Approach 2:
The patent implements periodic burst access patterns that align with the convolutional interleaver's delay line structure. Data is accessed in periodic bursts corresponding to the interleaver depth, maximizing memory bandwidth utilization while maintaining data protection integrity.
3Adaptability or versatility
If on-chip BRAM resources are used, then other applications are supported, but memory resources are limited for large interleavers
Solution Approach 1:
The patent transitions from the single dimension of on-chip memory capacity to a two-dimensional architecture combining limited on-chip BRAM for control with extensive off-chip memory for data storage. This dimensional expansion provides both application flexibility and sufficient memory capacity for large interleavers.
4Ease of manufacture
If flip-flops are used for delay lines, then implementation is straightforward, but silicon resources are consumed
Solution Approach 1:
The patent replaces the mechanical flip-flop-based delay line system with a memory-based system using external burst-capable memory. This substitution eliminates the need for extensive on-chip flip-flop resources while maintaining the delay line functionality through software-controlled memory access patterns.
Data Source
AI summary
A convolutional interleaver uses local memory of a first IC in combination with burst-type memory of a second IC. When a burst of data is read from memory of the second IC, one data value is provided to a data output and the remaining values are temporarily stored in local memory. After the memory of the second IC is initially filled, burst WRITE and burst READ operations provide efficient data transmission between the ICs.