Convolutional Interleaver Memory Layout for Cache-Efficient Throughput
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Solution Overview
Problem
Software implementations of convolutional interleavers face inefficiencies due to non-sequential memory access patterns, leading to suboptimal throughput, especially when compared to hardware implementations, and struggle to handle high data speeds effectively in real-time software-defined radio applications.
Innovation Solution
A high-throughput software-defined implementation of convolutional interleaving and de-interleaving algorithms is achieved by representing memory as a three-dimensional array, optimizing cache usage through specific indexing schemes and multithreading, allowing for efficient processing and interleaving of samples across multiple processor cores.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If convolutional interleaving is implemented using traditional software approaches with ring buffers, then the implementation is portable and flexible, but throughput is limited due to non-sequential memory access patterns
Solution Approach 1:
The patent transforms the traditional one-dimensional ring buffer into a two-dimensional array structure with M rows and N columns. This dimensional change enables sequential memory access patterns by organizing data such that consecutive elements in memory correspond to sequential operations in the interleaving algorithm, thereby achieving hardware-like throughput on general-purpose processors.
Solution Approach 2:
The patent divides the interleaving operation into M separate delay lines (rows), each processing N samples. This segmentation allows independent processing of multiple sample streams simultaneously, improving throughput by utilizing parallel memory access patterns while maintaining the convolutional interleaving functionality.
2Productivity
If hardware shift registers are used for convolutional interleaving, then throughput is maximized with single-clock-cycle delays, but portability and flexibility are reduced
Solution Approach 1:
The patent creates a software copy of the hardware shift register architecture by using arrays to represent delay lines. This copying approach preserves the functional behavior and throughput characteristics of hardware implementations while enabling portability to general-purpose processors and software environments.
Solution Approach 2:
The patent replaces the mechanical hardware shift register system with a software-based array structure that emulates the same functionality. This substitution maintains the high-throughput performance of hardware while gaining the flexibility and portability of software implementations on various processor architectures.
3Device complexity
If rectangular block interleavers are used instead of convolutional interleavers, then implementation is simpler, but latency increases and error correction performance deteriorates
Solution Approach 1:
The patent implements a dynamic interleaving structure where the delay line lengths are integer multiples of N, allowing flexible configuration of M and N parameters. This dynamic structure enables optimization of both latency and error correction performance by adjusting the delay line configurations, unlike fixed rectangular block interleavers.
Data Source
AI summary
High-throughput software-defined convolutional interleavers and de-interleavers are provided herein. In some examples, a method for generating convolutionally interleaved samples on a general purpose processor with cache is provided. Memory is represented as a three dimensional array, indexed by block number, row, and column. Input samples may be written to the cache according to an indexing scheme. Output samples may be generated every MN samples by reading out the samples from the cache in a transposed and vectorized order.