Convolutional Encoder Rate Matching with Identical Parity Interleavers

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Solution Overview

Problem

Conventional rate matching circuits for convolutional codes in mobile communication systems have high complexity and require different interleavers for different parity bit streams, limiting their efficiency and performance.

Innovation Solution

A method and apparatus for rate matching that uses identical interleavers for different parity bit streams, performing group multiplexing of parity bits to reduce complexity and improve channel encoding performance, allowing for flexible code rate adjustment by puncturing or repeating bits in a controlled order.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional rate matching circuits use different interleavers for different parity bit streams, then the performance of channel encoding is improved, but the device complexity increases

Engineering Contradiction:

Improvechannel encoding performanceVSAvoidencoder complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies universality by using a single interleaver structure that can handle multiple parity bit streams (P1, P2, P3) through group multiplexing. Instead of implementing separate interleavers for each parity stream, one interleaver is configured to process groups of bits from different streams in an interleaved manner, reducing device complexity while maintaining the performance benefits of interleaving.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If conventional rate matching circuits perform bit-multiplexing of interleaved bits from all parity bit streams, then the code rate can be adjusted to match channel requirements, but the device complexity increases

Engineering Contradiction:

Improvecode rate adjustment flexibilityVSAvoidrate matching circuit complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the bit multiplexing process into two stages: first, group multiplexing that outputs bits in group order (P1 group, then P2 group, then P3 group), and second, a simplified rate matching stage that selects bits from this grouped output. This segmentation reduces complexity compared to traditional bit-level multiplexing of all streams simultaneously.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies preliminary action by performing group multiplexing before the final rate matching operation. The interleaved parity bits are first organized into groups from different streams (P1, P2, P3 groups) in a predetermined order, and then the rate matching circuit selects from this pre-organized sequence. This preliminary organization simplifies the subsequent rate matching process.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS8607130B2Computationally efficient convolutional coding with rate-matching

Publication Date: 2013.12.10 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)

AI summary

An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.