Convolutional Code Rate Matching With Identical Parity Interleavers
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Solution Overview
Problem
Conventional rate matching circuits for convolutional codes in mobile communication systems have high complexity and require different interleavers for different parity bit streams, limiting their efficiency and performance.
Innovation Solution
A method and apparatus for rate matching that uses identical interleavers for different parity bit streams, performing group multiplexing and puncturing or repeating parity bits to match the data channel rate, while maintaining the order of parity bits within groups, reducing the complexity of the channel encoder and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional rate matching circuits use different interleavers for different parity bit streams, then the performance is improved, but the device complexity increases
Solution Approach 1:
The patent applies universality by using a single interleaver structure that can handle multiple parity bit streams (P1, P2, P3) from different convolutional code rates. Instead of requiring separate interleavers for each parity stream, one interleaver is configured to interleave all parity bits according to their group identifiers, thereby reducing device complexity while maintaining the ability to process diverse code rates effectively
Solution Approach 2:
The patent segments parity bits into different groups based on their source convolutional code rate (e.g., P1 from rate 1/3, P2 and P3 from rate 1/2). This segmentation allows the single interleaver to process different parity bit streams in an organized manner, preserving the performance benefits of separate handling while avoiding the complexity of multiple interleavers
2Adaptability or versatility
If rate matching circuits perform bit-multiplexing of interleaved bits from all parity bit streams, then the adaptability to different data transmission rates is improved, but the device complexity increases
Solution Approach 1:
The patent performs preliminary action by organizing parity bits into distinct groups based on their source code rate before the rate matching process. This pre-organization allows the rate matching circuit to selectively puncture or repeat bits from specific groups without requiring complex real-time decision logic, thereby reducing circuit complexity while maintaining adaptability to different data transmission rates
Solution Approach 2:
The patent implements dynamic rate matching by allowing the rate matching circuit to adaptively select which parity bit groups to puncture or repeat based on the required code rate. The circuit can dynamically adjust the output by controlling the selection of bits from different groups (P1, P2, P3) without requiring reconfiguration of the interleaver structure, thus maintaining versatility with reduced complexity
Data Source
AI summary
An error coding circuit comprises a non-systematic convolutional encoder for coding an input bit stream to produce two or more groups of parity bits, an interleaver circuit for interleaving parity bits within each group of parity bits, and a rate-matching circuit for outputting a selected number of the interleaved parity bits ordered by group to obtain a desired code rate.