Convolutional Rate-Matching Circuit With Unified Parity Interleaving
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Solution Overview
Problem
Conventional rate matching circuits for convolutional codes in mobile communication systems have high complexity and require different interleavers for different parity bit streams, limiting their efficiency and performance.
Innovation Solution
A method and circuit using a non-systematic convolutional encoder to produce three groups of parity bits, with an interleaver and rate-matching circuit that allows identical interleavers for different parity bit streams and outputs parity bits in group order to achieve a desired code rate, reducing complexity and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional rate matching circuits are used with different interleavers for different parity bit streams, then performance is maintained, but device complexity increases
Solution Approach 1:
The patent applies universality by using a single interleaver structure that processes multiple parity bit streams (P1, P2, P3) from the rate 1/3 convolutional encoder. Instead of implementing separate interleavers for each parity stream, the invention uses one interleaver that handles all three streams, reducing device complexity while maintaining the error correction performance through unified interleaving of all parity bits before rate matching.
2Device complexity
If identical interleavers are used for different parity bit streams, then device complexity is reduced, but performance may deteriorate
Solution Approach 1:
The patent merges the processing of multiple parity bit streams by combining them into a single interleaving operation. All three parity streams P1, P2, and P3 are fed into the same interleaver structure, which processes them together. This merging approach reduces complexity by eliminating redundant interleaver implementations while maintaining performance through unified error protection across all parity streams.
3Manufacturing precision
If rate matching is performed with high precision bit-multiplexing, then code rate accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the rate matching process into two distinct stages: first, interleaving of all parity bits within each group, and second, rate matching operations performed separately on each interleaved parity bit group. This segmentation allows the rate matching circuit to handle one group at a time rather than processing all bits simultaneously, reducing circuit complexity while maintaining precise code rate control through systematic puncturing or repetition within each segment.
Data Source
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AI summary
A communication terminal (10) for a mobile communications system and a method for a communication terminal (10) is disclosed. The communication terminal comprising an error coding circuit (24). The error coding circuit further comprises a non-systematic convolutional encoder (40) for coding an input bit stream (I) to produce three groups of parity bits (P1, P2, P3), wherein said encoder implements a rate 1/3 tail-biting convolutional code belonging to the class of maximum free distance codes with optimal distance spectra, such that a rate 1/2 code belonging to the class of maximum free distance codes with optimal distance spectra can be obtained by puncturing one of the groups of parity bits. The error coding circuit further comprises an interleaver circuit (42) for interleaving parity bits within each group of parity bits and a rate-matching circuit (44) for outputting (C) a selected number of said interleaved parity bits (P1', P2', P3') ordered by group to obtain a desired code rate.