Cooled Tape Frame Lift and Shadow Ring for Plasma Wafer Dicing
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Solution Overview
Problem
Current semiconductor wafer dicing methods, such as scribing and sawing, result in chipping and cracking issues, leading to waste of wafer real estate and inefficiencies, while plasma dicing faces cost and implementation challenges, particularly with metals like copper.
Innovation Solution
A hybrid method combining femtosecond-based laser scribing and plasma etching, with a cooled tape frame lift and actively-cooled shadow ring, to singulate integrated circuits, reducing thermal damage and enabling denser packing without the need for lithography patterning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scribing or sawing is used for wafer dicing, then the wafer can be separated into individual dies, but chipping and cracking occur along the severed edges
Solution Approach 1:
The patent replaces mechanical scribing and sawing systems with a plasma-based dicing system. The plasma process uses reactive ions to etch through the wafer material along predefined streets, eliminating mechanical contact that causes chipping and cracking. The plasma chemistry selectively removes material without the mechanical stresses inherent in traditional methods.
Solution Approach 2:
The patent changes the fundamental processing parameter from mechanical force to plasma energy. By controlling plasma power, gas flow, and exposure time, the process achieves precise material removal without mechanical contact. The plasma parameters are optimized to etch through the wafer thickness while maintaining edge integrity.
2Reliability
If additional spacing is required between dies to prevent damage, then chipping and cracking are reduced, but wafer real estate is wasted
Solution Approach 1:
The plasma dicing system enables tighter die spacing by replacing mechanical cutting with a contactless process. The plasma ions can be precisely directed to etch only along the street regions between dies, eliminating the need for large safety margins required by mechanical methods. This increases the number of dies per wafer.
3Reliability
If plasma dicing is implemented, then chipping and cracking are minimized, but cost increases due to lithography requirements
Solution Approach 1:
The patent applies a photosensitive mask layer to the wafer surface before plasma processing. This mask is patterned to define the street regions that will be etched. The preliminary masking step enables selective plasma removal only in the inter-die streets, protecting the die regions while achieving the dicing pattern.
Solution Approach 2:
The photosensitive mask serves as an intermediary between the plasma source and the wafer substrate. It selectively allows plasma ions to reach the street regions while blocking them from the die regions. This intermediary enables precise pattern transfer without requiring complex direct writing or lithography systems.
4Productivity
If plasma processing is used for copper metals, then dicing can be performed, but production issues and throughput limits occur
Solution Approach 1:
The patent optimizes plasma processing parameters specifically for copper-containing structures. By adjusting plasma power, gas composition, and pressure, the process achieves selective etching of dielectric materials while preserving copper interconnects. The plasma chemistry and parameters are tuned to prevent copper contamination and deposition issues.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes chipping and cracking, allows for denser integration of dies on wafers, and reduces processing costs by eliminating the need for costly lithography, while maintaining high precision and throughput.
Implementation Method 1
a cooled tape frame lift and actively-cooled shadow ring, to singulate integrated circuits, reducing thermal damage
Implementation Method 2
plasma etching, with a cooled tape frame lift and actively-cooled shadow ring, to singulate integrated circuits
Data Source
AI summary
Methods of and apparatuses for dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a tape frame lift assembly for a plasma processing chamber includes a capture single ring having an upper surface for supporting a tape frame of a substrate support and for cooling the tape frame. The tape frame lift assembly also includes one or more capture lift arms for moving the capture single ring to and from transfer and processing positions. The tape frame assembly also includes one or more captured lift plate portions, one captured lift plate portion corresponding to one capture lift arm, the one or more captured lift plate portions for coupling the one or more capture lift arms to the capture single ring.