Cooperative Memory Controller for Host Request Load Balancing
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Solution Overview
Problem
In non-volatile memory systems, memory controllers may experience delays in responding to host requests due to operational issues or when performing other tasks.
Innovation Solution
A memory system with a cooperative controller that manages state information from multiple memory controllers, allowing another memory controller to process host requests if the primary controller is experiencing issues or busy with other operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single memory controller is used to manage host requests, then the system structure is simple, but response delay occurs when the controller is busy or experiencing problems
Solution Approach 1:
The patent divides the memory controller function into multiple independent memory controllers (first memory controller and second memory controller), each capable of independently receiving and processing host requests. This segmentation allows one controller to handle requests while another is busy or experiencing issues, eliminating response delays without significantly increasing overall system complexity.
Solution Approach 2:
The patent introduces a load balancing mechanism that dynamically changes the operational state distribution between multiple memory controllers. By monitoring which controller is available and assigning requests accordingly, the system optimizes resource utilization and ensures continuous response capability without requiring complex failover procedures.
2Productivity
If multiple memory controllers share namespaces, then host request processing capability is improved, but coordination complexity increases
Solution Approach 1:
The patent assigns distinct namespaces to different memory controllers (first namespace to first memory controller, second namespace to second memory controller), allowing independent request processing without complex coordination. This segmentation approach maintains high productivity while simplifying the coordination mechanism by eliminating namespace conflicts.
Solution Approach 2:
The patent introduces a host as an intermediary that receives requests from external devices and distributes them to appropriate memory controllers based on namespace mapping. This intermediary approach simplifies controller coordination by centralizing the decision-making at the host level rather than requiring direct complex communication between controllers.
3Use of energy by moving object
If a memory controller processes all host requests, then the controller is fully utilized, but response time increases when performing other operations
Solution Approach 1:
The patent divides the workload between multiple memory controllers, allowing each controller to process requests independently without waiting for the other. This segmentation enables parallel processing that maintains high operational efficiency while reducing response time by eliminating sequential dependencies.
Solution Approach 2:
The patent implements a mechanism where the host pre-determines which memory controller should handle a specific request based on namespace information before the request reaches the controllers. This preliminary assignment allows controllers to be pre-positioned for optimal response without requiring real-time coordination or waiting for other controllers to complete operations.
Data Source
AI summary
Disclosed is a memory controller including: a first external interface controller configured to communicate with a first external device and to receive a second external device access request message from the first external device; a second external interface controller configured to communicate with a second external device; a third external interface controller configured to communicate with a third external device, wherein the third external device is connected to a plurality of memory controllers, receive and store state information from the plurality of memory controllers, and determines a memory controller among the plurality of memory controllers for the second external device access request; and a main controller configured to determine, based on its state information, whether to process the second external device access request by itself or by another one of the plurality of memory controllers.