Hardware-Software Cooperative Pipeline Error Detection
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Solution Overview
Problem
Compute-class processors face challenges in detecting pipeline errors in register file storage due to coverage holes left by ECC codes, requiring additional mechanisms that incur high costs or complexity, especially in compute-intensive processors like GPUs.
Innovation Solution
Implementing software-hardware cooperative mechanisms for intra-thread duplication that leverage register file error detection hardware to implicitly check data from duplicate instructions, reducing overheads and providing low-latency error detection with modest hardware modifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spatial duplication is used to protect against pipeline errors, then reliability is improved, but device complexity and chip area cost increase significantly
Solution Approach 1:
The patent employs temporal duplication by executing instructions twice (original and shadow instructions) and comparing results, rather than using spatial duplication with duplicate hardware pipelines. This copying approach achieves error detection through result comparison while avoiding the need for duplicate pipeline hardware, thus improving reliability without proportionally increasing device complexity.
Solution Approach 2:
The patent replaces the mechanical hardware-based error detection (spatial duplication with duplicate pipelines) with a software-based approach (temporal duplication with instruction replay and result comparison). This substitution reduces hardware complexity while maintaining error detection capability through software-controlled execution and comparison logic.
2Reliability
If temporal duplication with explicit checking instructions is used, then reliability is improved, but productivity decreases due to program bloat and performance overhead
Solution Approach 1:
The patent enables the error detection mechanism to operate transparently without requiring explicit checking instructions in the program. The shadow instruction execution and result comparison are automatically performed by the hardware system, allowing error protection to occur without programmer intervention or additional explicit checking code, thus reducing program bloat and maintaining better execution performance.
Solution Approach 2:
The patent performs error detection by executing shadow instructions concurrently or in advance and comparing results before the original instruction completes. This preliminary action allows error detection to occur without adding significant overhead to the critical path, as the comparison is prepared in advance rather than waiting for instruction completion.
3Reliability
If specialized concurrent checkers are used to protect pipeline operations, then reliability is improved, but device complexity and area cost increase
Solution Approach 1:
The patent uses a universal error detection mechanism that handles multiple pipeline operations (arithmetic, logic, memory) through a single shadow instruction execution and comparison framework. Rather than implementing specialized checkers for each operation type, the system uses a general-purpose temporal duplication approach that works across all pipeline stages, reducing design complexity while maintaining comprehensive error detection.
Data Source
AI summary
A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.