Cooperative Warp Scheduling for Register Conflict-Free Vector Computing

The patent segments the general-purpose register file into multiple independent banks (e.g., even banks and odd banks). Different warps are directed to access different banks simultaneously, allowing parallel register access without conflicts. This segmentation enables multiple warps to execute instructions in parallel without stalling the pipeline, thus maintaining high processing speed while eliminating access conflicts.

The patent implements dynamic register bank assignment where the scheduler can flexibly assign different register banks to different warps based on their specific data dependency requirements. This dynamic allocation allows the system to adapt to varying computational patterns, maximizing pipeline utilization while maintaining manageable resource complexity through systematic assignment rules.

The patent introduces a warp scheduler as an intermediary component that manages parallel warp execution. The scheduler coordinates register bank assignments and instruction dispatch to multiple warps, enabling efficient parallel processing while centralizing the coordination logic. This mediator approach allows warps to execute independently with high efficiency while the scheduler handles coordination overhead systematically, preventing race conditions and ensuring correct execution order when needed.